=============================================================================
Intel(R) Server Platforms SE7320SP2/SE7525GP2 BIOS RELEASE NOTES
=============================================================================
INTEL Enterprise Platform & Services Marketing
Intel Corporation
2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA
=============================================================================
DATE: 		Mar. 24, 2006
TO:		Intel Server Platform SE7320SP2/SE7525GP2 Customers
SUBJECT:	BIOS Release Notes: P.11 (build 043)
=============================================================================
Information in this document is provided in connection with Intel products. 
No license, express or implied, by estoppel or otherwise, to any intellectual 
property rights is granted by this document. Except as provided in Intel's 
Terms and Conditions of Sale for such products, Intel assumes no liability 
whatsoever, and Intel disclaims any express or implied warranty, relating to 
sale and/or use of Intel products including liability or warranties relating 
to fitness for a particular purpose, merchantability, or infringement of any 
patent, copyright or other intellectual property right. Intel Corporation may 
have patents or pending patent applications, trademarks, copyrights, or other 
intellectual property rights that relate to the presented subject matter. The 
furnishing of documents and other materials and information does not provide 
any license, express or implied, by estoppel or otherwise, to any such 
patents, trademarks, copyrights, or other intellectual property rights.  
Intel products are not intended for use in medical, life saving, or life 
sustaining applications. Intel may make changes to specifications and product 
descriptions at any time, without notice.

Intel is a registered trademark of Intel Corporation. 

*Other names and brands are the property of their respective owners.

Copyright(c) 2004 Intel Corporation.

=============================================================================
                              ABOUT THIS RELEASE
=============================================================================
Build #		: 043
Build Stamp	: SE7320SP20.86B.P.11.00.0043.032420060930
		  SE7525GP20.86B.P.11.00.0043.032420060930
		  
Build Date	: 24 Mar. 2006

=============================================================================
                           BIOS COMPONENTS/CONTENTS
=============================================================================
Processor stepping(s) supported: Intel(R) Xeon(TM) Processors MP

Microcode Versions:
Filename     | Description                  | Stepping(s)    				 |
-------------+------------------------------+---------------------------------------------
M1DF3417.TXT | Assembly format, Revision 17 | D-0 Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache|
MBDF4117.TXT | Assembly format, Revision 17 | E-0 Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache|
M9DF4305.TXT | Assembly format, Revision 05 | N-0 Intel(R) Xeon(R) 800MHz FSB/2M L2 Cache|
MBDF4903.TXT | Assembly format, Revision 03 | G-1 Intel(R) Xeon(R) 800MHz FSB/2M L2 Cache|
M5DF4A02.TXT | Assembly format, Revision 02 | R-0 Intel(R) Xeon(R) 800MHz FSB/2M L2 Cache|

System hardware configurations supported: SE7320SP2/SE7525GP2 revision FAB 5/6 (Production)

=============================================================================
                       SYSTEM FIRMWARE REQUIREMENTS/REVISIONS
=============================================================================
BIOS Update Utility
AMI AFU	: 1.33
BMC FW	: mBMC FW 2.31 or later
BMC CFG	: 1.20 or later
FRU/SDR	: FRUSDR 1.30 or higher

On-Board Component option ROM Versions:
ICHR SATA RAID    : 5.3.07061155I
NIC 82541GI	  : v1.2.22
ATI Rage XL VGA   : GR-xlamis3y.330-4.333

=============================================================================
             SYSTEM FIRMWARE REVISIONS TESTED AT TIME OF RELEASE
=============================================================================
- PC87431M mini-Baseboard Management Controller (mBMC): FW Revision 2.40
- SE7320SP20/SE7525GP20 FRU/SDR package: Revision 1.30

=============================================================================
                           IMPORTANT INSTALLATION NOTES
=============================================================================
IMPORTANT NOTES:


1.	There are 2 methods to flash BIOS.
	1.1 Method 1:
	(1) Copy all of the following files into the same folder in Hard Drive
	    or bootable USB Disk Key :
	    BIO\1.bat
	    BIO\AFUDOS.exe
	    BIO\P11.rom

	(2) Go to this folder to run 1.bat and update finishes automatically.	
	
	The update will show seven progress status as follows:

	Reading file .......... done
	Erasing flash ......... done
	Writing flash ......... done
	Verifying flash ....... done
	Erasing BootBlock ..... done
	Writing BootBlock ..... done
	Verifying BootBlock ... done

	1.2 Method 2:
	(1) Go to BIN folder and execute P09.EXE to make bootable floppy.
	(2) Use this bootable floppy to boot and update finishes automatically.	
	

2.	After system boots, enter BIOS Setup if you want to change any options.


*****************************************
*** USB-Disk Recovery Feature Details ***
*****************************************
- Build Recovery Storage
  1.    Plug in the USB DISK_ON_KEY
  2.    Boot the system to DOS on a bootable floppy
  3.    Then from the floppy, format the USB DISK_ON_KEY to FAT 12 or FAT 16
  4.    Rename ROM file to AMIBOOT.ROM and copy it to USB DISK_ON_KEY.

- Execute BIOS Recovery
  1.    User Forced Recovery
        - set Recovery Boot Jumper J17 (10-11)
        - Insert the Recovery storage into USB port.
        - Power on system
        - System boot and the debug port will display the flash progress.
        - When flash complete, power off system and set jumper back to Normal
          mode J17 (9-10)

  2.	Auto Recovery
        - If system ROM is damaged (checksum BAD), system will perform BIOS
          recovery automatically.

**NOTE** : The recovery only supports the storages of both type FAT12 & FAT16.

**********************************************
*** Multi-Disk Recovery Feature Details ***
**********************************************
With this new feature the System Recovery can be made from Multiple Floppy
Disks to support ROM image greater than 1MB. 

- Build Recovery Storage
  1.	Use the Split.exe file to split the ROM image.
	- Use the following command syntax at the command prompt
	- split <File Name To Be Split>  <New File Name>  <File Size in KB>

	- For Example
	- C:\split AMIBOOT.ROM AMIBOOT 1024

  2.	The above command will create the Files of sizes 1MB each (1024KB) 
  	with names AMIBOOT.000, AMIBOOT.001¡K and so on depending upon the
  	AMIBOOT.ROM file size.

- Execute BIOS Recovery
  1.    User Forced Recovery
        - set Recovery Boot Jumper J17 (10-11)
        - Load the first Disk AMIBOOT.000 in floppy
        - Power on system
        - System boot and the debug port will display the flash progress.
        - Load AMIBOOT.00x finish. System beep......
        - Replce the next disk AMIBOOT.00x in floppy
        - When flash complete, power off system and set jumper back to Normal
          mode J17 (9-10)

  2. 	Auto Recovery
        - If system ROM is damaged (checksum BAD), system will perform BIOS
          recovery automatically.

- Multi-Disk Recovery Beep Code List:
  This uses the standard beep codes used by AMI Core8 for Recovery with some
  additional codes. They are¡K (each beep is 1sec long with 0.5sec gap)
  1 long beep	Insert for AMIBOOT.001 File
  2 long beeps	Insert for AMIBOOT.002 File
  3 long beeps	Insert for AMIBOOT.003 File
  ¡K¡K¡K¡K¡K¡K¡K¡K¡K¡K¡K¡K¡K.

- Multi-Disk Recovery limitations:
  Maximum Files supported 1000 files (AMIBOOT.000 to AMIBOOT.999)

***********************************************
***  AMI AFUDOS Flash Feature Details  ***
***********************************************
- AFUDOS.EXE V1.33
- This update processing takes 3 to 4 minutes.  Never turn off the system 
  during the update processing. The following message appears when the update 
  processing is finished:

	Reading file ........ done
	Erasing flash ....... done
	Writing flash ....... done
	Verifying flash ..... done
	Erasing BootBlock ... done
	Writing BootBlock ... done
	Verifying BootBlock.. done

  If the system does not restart, TURN THE POWER OFF, THEN ON.

AMI Firmware Update Utility - Version 1.33
Copyright (C)2004 American Megatrends, Inc.  All rights reserved.

	afudos /i<ROM filename> [/o<save ROM filename>] [/n] [/p[b][n][c]]
	[/r<registry_path>] [/s] [/k[N]] [/q] [/h]

	/n    - don't check ROM ID
	/pbnc -
		b - Program Boot Block
		n - Program NVRAM
		c - Destroy System CMOS
	/r    - registry path to store result of operation (Windows version)
	/k    - Program all non-critical block only
	/kN   - Program N'th non-critical block only (from k0/k1/k3 upto k7)
	/c    - Skip non-critical blocks
	/s    - Leave signature in BIOS
	/q    - Silent execution
	/h    - print help
	/t    - Display ROM ID string
        /c    - Program Main BIOS and all Non-critical blocks
        /cN   - Program Main BIOS and N'th Non-critical block (from c0 upto c7)
        /d    - Compare ROM file (skips flashing)
        /u<filename>	-Display ROM ID

=============================================================================
                            KNOWN ISSUES/WORKAROUNDS
=============================================================================
- When running the Flash Utilities (AFUDOS, AFUWIN etc ) do not use the
  following options

	/pn   - for flashing NVRAM Block
	/k    - for flashing all Non-Critical Blocks only
	/c    - for flashing all Non-Critical Blocks along with main BIOS image
	/k0   - for flashing the Non-Critical Block 0 only
	/c0   - for flashing the Non-Critical Block 0 along with main BIOS
	        image

  Since the above options try to flash protected areas NVRAM or Non-Critical
  Block 0 the verification fails.

  Always use the following command to flash a bios

	C:\afudos /iXXXX.ROM /pb /c1 /c2

	/i    - Input .ROM file
	/pb   - Flash Boot Block
	/c1   - Flash Non-Critical Block 1 (OEM Logo & User Binaries) along
	        with Main BIOS Image
	/c2   - Flash Non-Critical Block 2 (CPU MicroCode) along with Main BIOS
	        Image

- If user update to Rolling BIOS image (Build 009: A02 or after) then it can't
  flash back to non Rolling BIOS image (Build 008: A01 or before).

- If user would like to update BIOS from non Rolling BIOS image (Build 008: A01
  or before), please use BIOS version 2B00 (Build 010: BC01) and type '1' to
  flash BIOS.

- BIOS version BC02 or below does not support MCH C-0 stepping.

- BIOS version BC04 or below does not support IA-32e enabled CPU.

- BIOS version RC01 or above does not support MCH B-0 or before.

- The recovery mode support FAT12 and FAT16 only.

- SE7320SP2/SE7525GP2 do not allow flash utility to update NVRAM.

- The BIOS setup item "Maximum CPUID Value Limit" must be enabled for
  installing some legacy OSes (NT4.0 for example) which do not support it.

- If user updates BIOS to RC02 (Build: 25)  then it may not flash back to P04
  (Build :24 or before).

- If user want updates BIOS to P05 (Build: 28) from RC02 (Build: 25 or before).
  Please flash BIOS twice to make sure both banks' BIOS are the same. 
  Cause by the Rolling BIOS procedure changed.

- If user want to downgrade BIOS from P05 to P04. There have two Methods as 
  following.
Method A 
1. Power off system
2. Change the Rolling BIOS jumper J29 to 2-3 (force BIOS to lower bank)
3. Power on system
4. Flash BIOS P04
5. Reboot system
(This will cause the 0xFFC00000 ~ 0xFFDFFFFF equal to 0xFFE00000 ~ 0xFFFFFFFF 
 and they are always the lower bank of flash ROM.)

Method B (If user flash P04 but system is always P05)
1. Flash BIOS P05 again
2. Reboot system
3. Flash BIOS P04
4. Reboot system
(This will change the P05 BIOS from lower bank to upper bank of flash ROM and 
 be successful to update BIOS to P04.)  

=============================================================================
                              FEATURES ADDED
=============================================================================
Build 043: P.11
- Rebuilt BIOS P.11 based on P.11

Build 042: RC01.11
- CCB item #342 Add platform checking capability to OFU utility.
- Update LSI for Hance Rapids (6300ESB) SATA RAID to 5.4.10281401I.

Build 041: P.10
- Rebuilt BIOS P.10 based on RC01.10

Build 040: RC01.10
- Added processor mixed Voltage combinations Feature.
- Added Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache G-1 microcode Revision 3.
- Integrated E7520_Error_reporting_rev027.

Build 039: P.09
- Removed Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache G-1 Processor Microcode.

Build 038: RC01.09
- Updated Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache D-0 microcode to Revision 17, 
  updated Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache E-0 microcode to Revision 17, 
  updated Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache N-0 microcode to Revision 05.
- Added Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache G-1 microcode Revision 3, and 
  added Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache R-0 microcode Revision 2.
- Updated AMI TAG CORE0195(Date: Tue 05-03-2005)
- Latest Mixed Processor Stepping Changes.
- Least Featured BSP Changes.
- Implement WOL from S5 option in BIOS setup.
- MAX Payload size of PCI-E transactions and Read Request Size from 128 to 256.
- Updated USB module to 8.00.04_USB-2.24.00-Beta5.
- Updated AMI TAG USB0089.3, USB0100, USB0107, USB0109, USB0111, USB0112.
- PCI express error reporting SERR setting.
- Set the region F0000 as memory-mapped and un-cacheable.
- Set the Echo TPR Disable bit (CPU MSR 1A0h bit 23) for Intel(R) Xeon(R) 800MHz 
  FSB/1M L2 Cache R-0 processors.
- Followed E7520_BSU_v1_07.pdf clarification #1 for recommended register 
  settings.

Build 037: P.08
- Rebuilt BIOS P.08 based on RC02.08

Build 036: RC02.08
- Added new options on the PCI Configuration Sub-menu to force PCI devices to 32 
  or 64bits and control the hightest PCI memory address.
- Fixed GV3/DBS function can not work when Hyper-Threading is disbaled.
- Fixed Power Button wakeup from S1 fail when IST enabled.
- Added POST error message when LV Noccna processor mixed stepping changes.
- Followed AMIBIOS CORE 8.00.11 to update Kernel code AMI TAG CORE0192.

Build 035: RC01.08
- Shaded 'Clear User Password' if user password is not installed.
  Shaded 'Set User Password' if Administrator Password is not installed.
  If Administrator password is cleared then User password is also cleared.
- Display the Hardware Prefetcher (Q_HW_Prefetcher) and Adjacent Cache Line 
  Prefetch (Q_ACL_Prefetch) to CPU menu.
- Bug Fixed for that BMC timestamp synced by BIOS being off by one day issue 
  seen with 2005 date.
- Enabled the TM2 for 3.6 GHz Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache Processors 
  with FSB 800MHz and procesor signature >= F40h.
- Updated the ISM module to ISM_00_01_04 from ISM_00_01_03.
- Fixed the system keeps rebooting without video when installed with Mixed 
  Processors.
- Udpated AMI TAG CPU40062 to improved 4G above memory issue.
- Updated AMI TAG CORE0155, CORE0155.1, CPUP40059, CPUP40018.03, CORE0135, 
  USB0095, USB0046.1, CORE0170, USB0032.1, USB0090.1, CORE0174, USB0097, 
  USB0089.1, USB0098, USB0094.1, CORE0180, IDE0030, 
- Bug fixed the NMI malfunctioning.
- CCB item #282 (Remove Event #0x83 from mBMC SEL) implemented.
- CCB item #290 F2 Setup Option requested to automatically clear mBMC SEL when 
  full.
- Prevented the PCI_INFO from overlapping.
- Do not log the Memory Buffer error because it is non-fatal error.
- Updated Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache E-0 microcode to Revision 12.
- Updated multi-language strings.
- Added logic "if reserve VPD also FFh, don't bother updating main".
- Bug fixed for SMBIOS Type0 BIOS Characteristics.
- Fixed the system hangs in various locations during POST when PTC card test is 
  running for test 13, 1.1, 1.2, 3.x.
- Bug fixed: memory end address in SMBIOS type17 are incorrect.
- Bug fixed: Unix floppy boot issue from Kraftway.

Build 034: P.07
- Rebuilt BIOS P07 based on RC01.07

Build 033: RC01.07
- Updated AMI Core label CORE0040/CORE0041/CORE0042.x for CMOS checksum issue.
- Updated AMI label CPU40056 for ILFBP module issue.
- Updated AMI TAG CPUP40057 (Tus 12/13/04)
- Followd AMIBIOS CORE 8.00.11 to update Kernel code.
- Updated the ISM module to ISM_00_01_03
- Updated Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache N-0 microcode to Revision 4.
- Updated Rolling BIOS to Beta8 from Beta7.
- Intel's formal recommendation for enabling LRU be that we clear all bits 13:0
  in R4Ch in Device8
- Upgraded the IST module to 8.00.10_IST_09A from 8.00.10_IST_09.
- Implemented E7520_BSU_v1.02 erratta #30: PCI EXpress x16 Graphics cards hang 
  during system boot.
- Implement E7520_BSU_v1_02 erratta#32. Memory Reference Code not recognizing 
  Address/Command Parity capable ECC DIMMs
- Fixed the Retaining configured boot order adding new device at end.
- Fixed the 'userBeforeOptionRomInit' is not executed before option ROM 
  initializing.
- Fixed that if the P-BIOS checksum is bad, it will force to recovery but not 
  toggle to the S-BIOS.
- Fixed the NVRAM "Update Failed" message appears even when NVRAM is not used.
- Fixed the USB 1G flash drive issue.
- Bug fixed (ref. ISSUES FIXED section)

Build 031: P.06
- Rebuilt BIOS P06 base on RC02.06
- Removed Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache N-0 microcode microcode 
  patch in P06 BIOS

Build 030: RC02.06
- Bug fixes (ref. ISSUES FIXED section)

Build 029: RC01.06
- Updated AMI TAG CORE0138 / CORE0139 (09-10-2004)
- Fixed the system sometimes will hang After execute STI instruction in 
  procedure imtProtectedModeEntryPoint.
- Modified PCIE error handling service to support error detection on all root 
  ports.
- Followed AMIBIOS CORE 8.00.11 to update Kernel code.
- Fixed the CMOS clear function by mBMC displaying wrong POST message issue.
- Updated Rolling BIOS to Beta7 from Beta5.
- Updated DOSCMOS eModule to DOSCMOS_00_00_04.
- Fixed some exact timing and display mode issue in Console Redirection mode.
- Fixed the CPU SpeedStep display string to (TM) from tm.
- Updated CPU module from 8.00.00_CPU-P4_3C.07 to 8.00.00_CPU-P4_3C.08.

Build 028: P05
- Rebuilt BIOS P05 base on RC04

Build 027: RC04.05
- Bug fixed (ref. ISSUES FIXED section)
      
Build 026: RC03.05
- Bug fixed (ref. ISSUES FIXED section)

Build 025: RC02.05
- Supported AMI DMI edit tool (v2.00.33) to change SMBIOS Type11 (OEM String) 
  information.
- Updated EFI WW14, WW22 and WW30 drops.
- Changed the 'Quiet Boot' default setting from 'Disabled' to 'Enabled'.
- Updated the SiI3124 Optrom to 6017 from 6015.
- Updated the 6300ESB Oprom to 5.3.07061155 from 5.3.04191453.
- Updated onboard NIC 82541GI optrom to 1.2.22 from 1.2.19.
- Used PCI SERR to log PCI-E Uncorretable ERROR.
- Followed the SE7320SP2/SE7525GP2 EPS v1.01 to implement FSB/Hublink/MBUF SEL.
- Updated the E7520 memory reference code to v1.04 from v1.03.
- Updated CPU module to 8.00.00_CPU-P4_3C.07 from 8.00.00_CPU-P4_3C.02.
- Updated IST ICH to 8.00.10_IST_09A from 8.00.10_IST_09.
- Implemented the latest drop(ASD_07072004) of multi-language.
- Implemented the ACPI MCFG table for PCI Express.
- Integrated E7520_Error_reporting_rev023.
- Added No-Execute (NX) Memory Protection Technology to BIOS Setup Option and
  default setting is disabled.
- Followed SE7320SP2/SE7525GP2 EPS v1.01 to change the BIOS Recovery behavior 
  from reset to halt when BIOS Recovery is completed.
- Sent chassis reset command to mBMC to perform warm reset.
- Integrated Rolling BIOS Beta4 and Rolling BIOS watchdog will stop at
  checkpoint 0x03.
- Enhanced Halt State (C1E) is enabled if pcocessor supports this feature.
- Supported recovery from USB CDROM and USB floppy.
- Do not force PIRQA-D routing to IRQ7 if the MCH stepping is C4 stepping.

Build 024: P04
- Followed E7520_BSU_v0_82.pdf to fix MCH IRQ Hang issue.
- Redirected SATA IRQ handler entry point from F000h block to E000h.It can solve
  SATA IRQ7 issue.
- Since SE7320SP2/SE7525GP2 used IRQ9 as SCI, removed SCI IRQ (IRQ9) from PIRQ(G).
- Displayed E7520 stepping in SETUP under Main Menu Options page.

Build 023: P03
- N/A

Build 022: P02
- Removed the E7520 string from POST diagnostic screen.

Build 021: P01
- Removed the evaluation string from POST diagnostic screen.
- Hid the 'Preproduction Debug' in BIOS setup menu.
- Fixed the incorrect string in the 'Processor Configuration' setup menu.
- Fixed the incorrect string when all DIMMs mark as failed.

Build 020: RC01.01
- Updated the Memory Reference Code to v1.03 from v1.02.
- Updated Intel security to IntelSecurity_00_00_17 from IntelSecurity_00_00_14.
- Updated the Intel Server management to ISM_00_00_97 from ISM_00_00_94.
- Used secondary non-critical block #2 for INT15 D042h to update CPU microcode.
- Updated IST to 8.00.10_IST_09 from 8.00.10_IST_08A.
- Updated MPS-Table eModule to 8.00.09_MPSTable_11 from 8.00.09_MPSTable_06.
- Updated the onboard NIC 82541GI option ROM to v1.2.19 from v1.2.17.
- Indegrated EFI eModule EFILH041704 and EFILH050604.
- Prevented UUID lost when 1st build in manufacture and battery lost.
- Allowed using PnP function to update SMBIOS type 11.
- Moved the USB data area to E000h segment because E7520 stepping C0 or above
  had fixed 'E7520 master aborts inbound accesses between 640KB and 1MB'.
- Updated the TControl value offset to 47 from 50 degrees Celsius.  

Build 019: B02
- Followed SE7320SP2/SE7525GP2 EPS v0.94 to modify the Error Code, Message and 
  Attribute for BIOS POST error message.
- Updatee 6300ESB SATA RAID option ROM to 5.3.04191453 from 5.2.02201602.
- Allowed ASL code to send debug code to 80port.
- Do not disable MBE when SBE 10 times within 1 hour.
- Followed Intel's recommendation to implement the workaround for 'ICH5/ICH5R 
  and 6300ESB USB Eye Diagram Issue'.
- Updated CPU module 8.00.00_CPU-P4_3C.02 from 8.00.00_CPU-P4_3C.01.
- Updated the Memory Reference Code to v1.02 from v1.00.
- Implemented the BSU v0.78.
- Implemented the Spare DIMM failover usage model and follow the BSU v0.78
  to implement the SPARECTL SEC prescale value/unit and threshold.
- Implemented the multi-language but it is not completed.
- Removed Compatibility Mode for PCI Express 1.0 and 1.0a Link Training for MCH
  C1 stepping or above.

Build 018: B01
- Updated E7520 Memory Reference Code to v1.00 from v0.86.
- Updated CPU module 8.00.00_CPU-P4_3C.01 from 8.00.00_CPU-P4_3C.00.
- Supported MMIO64 feature to allocate PCI resource above 4GB.
- Followed SE7320SP2/SE7525GP2 EPS v0.94 to implement setup menu.
- Implement E7520, E7320, E7525 MCH BIOS Specification Update v0.77.
- Changed CMOS date behavior to "System date will be set to build date if CMOS
  power loss or invalid date/time." from "System date will be set to build date
  whenever CMOS is bad.".
- Updated SETUP.BIN to v2.56 from v2.53 to support MenuItem shaded function!
- Don't execute PCI-E Jitter tolerance algorithm if MCH is C1 stepping.
- Updated Rolling BIOS module to Beta3 from Beta2 and reserved the Non-Critical
  Block2 for CPU uCode update from INT15 with AX=0xD042, BL=0x01.
- Used Critical Interrupt with Bus Correctable Error event to implement PCI
  Express error. (Event Data2 = Bus number, Event Date3 = Dev/Fun) before
  Intel finialized the PCI-E event log format.
- Do not log SBE event.

Build 017: BC08
- Updated IST to 8.00.10_IST_08A from 8.00.10_IST_08
- Changed the NVRAM to Secondary BIOS from primary BIOS.
- Implemented the IBIOSI ID identifying for Rolling BIOS.
- Rolling BIOS watchdog timer started on each booting.
- Supported baudrate of 38.4K for Serial Console redirection.
- Showed individual DIMM instead of Device Set for SMBIOS type17 'Size' field.
- Enabled PCI Express Bridge #2, #3, #4 for MCH C1 stepping.
- Implemented 'Port 60/64 Emulation' to USB configuration.
- Followed Intel Setup Spec to modify 'Processor Configuration' Setup sub-menu.
- Followed Intel Spec to modify 'Event Log' Setup sub-menu.
- Followed BSU v0.76 to change MCH D8-DB register to 0B5930000h from 0D5930000h.
- Updated Chipset error reporting following INTEL HW DEs guide lines.
- Do not log Single Bit Error event log.
- Raised NMI if Multi-Bit error detecting.
- Supported MMIO64 feature.
- Implemented FORCEPR# for Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache processor.
- Used BOARD ID instead of SIO3 revision ID to detect FAB5 M/B in bootblock.
  (BC07 use SIO3 A3 stepping to detect FAB5 M/B)

Build 016: BC07
- Integrated Intel Rolling BIOS Drop2 to SE7320SP2 BIOS.
- Made recovery behavior the same as 'AFUDOS /i<filename> /pb /c1'.
- Updated the SiI3124 Optrom to 6015 from 6014.
- Turned off the clock if the slot/device is empty.
- Automatic detecting hardware revision FAB5 and changed the behavior of
  Diag LED and DIMM Failed LED.
- Supported Zip-250 and Zip-750 in recovery mode.
- Followed Intel spec to modify SMBIOS Type 4/8/9/12/17.
- Followed Intel Spec to modify BIOS Setup Menu.
- Followed Intel Spec to modify FRB-2 & FRB-3 policy.
  (User should use 'ipmitool 84 18 52 11 00 00 20 00 8C F0' to enabled FRB3
  with countdown value = F0h = 240*100 ms = 24 seconds because SDR Package 0.55
  or before does not enabled FRB3.)
- Base on the test result, modified the PHY register of SiI3124.
- Implemented Lindenhurst/Lindenhurst-VS/ Tumwater MCH BIOS Spec update v0.75.

Build 015: BC06
- Updated the Intel memory reference code to 0.86x from 0.84x.
- Implemented the Userflash to support 64KB user binary.
- Implemented the Boot Intragrity Services (BIS).
- Implemented the DOSCMOS.

Build 014: BC05
- Implemented E7520/E7320/E7525 MCH BIOS Spec update v0.72.
- Supported dual monitor.
- Supported IA-32e.
- Followed EPG BIOS IBIOSI Specification v0.2 to implement IBIOSI feature.
- Disabled the unused Pin# in the clock generator.

Build 013: BC04
- Implemented the memory buffer error log.
- Implemented the PCI Express error log.
- Implemented E7520/E7320/E7525 MCH BIOS Spec update v0.71.
- Updated EFI module to EFI_00_00_30.
- Implemented the BIOS ID to setup menu.
- Removed SMBIOS type 24.

Build 012: BC03
- ATAPI CDROM recovery was supported.
- Updated the Memory Reference Code to 0.8x from 0.81.
- Video was not supported during BIOS Recoverys.
- Prevented BIOS Recovery to flash boot block.
- Replaced full reset with GPIO reset to prevent system shutdown then power on.
- Update 6300ESB SATA RAID option rom to 5.2.02201602 from 5.2.02031259.
- Update the SiI3124 SATA option rom 6014 from 6006.
- Follow E7520/E7320/E7525 MCH BIOS v0.71 to Implement a CMOS option for user 
  to change bits 10:7 of D0:F2:R9C-9Fh, from a value ranging 4 through 12.
- Implemented the BIOS ID to Smbios type 0.
- APM supported.

Build 011: BC02
- Changed the boot block recovery target to secondary bank from primary bank
  and boot block recovery will also program the boot block of secondary bank.
- Implemented 6300ESB Southbridge PCI Mode Performance Settings WhitePaper v1.5.
- Modified 6300ESB B0:D1E:F0 Register 50h, bit 13 to 1 to prevent LAN from
  disconnecting.
- Followed BIOS EPS v0.7 to implement IDE setup modification.
- Removed Processor Retest Setup Question because mBMC does not supported.
- Implemented a way to disable this workaround via a CMOS setup option
  ¡§Disable PCI Expres jitter tolerance¡¨.
- Changed the 6300ESB option rom to 5.2.02031259 from 5.2.12161343.
  This OPROM avoid using 640KB ~ 1MB memory range for read/write DMA command.
- Changed the DIMM falied LED for hardware revision FAB4.
- Displaied the setup option to select PCI Express v1.0 compliant for MCH B0
  stepping only.
- Followed mBMC EPS v0.9 to modify the PEF filter number of FP NMI button to 
  #7 from #9.
- Implemented POST_STATUS signal goes high to let the RMC card to know that BIOS
  is finished with its processes and the RMC is clear to begin its processes.
- Enabled FAN channel 0/2/3/4 in SIO3 for mBMC to monitor the FAN status.

Build 010: BC01
- Disabled the Dynamic Bus Inversion for A-Step MCH silicon and enable the
  Dynamic Bus Inversion for Non A-Step MCH silicon.
- Updated SEL_XOR ( BIOS_SEL XOR) selected code in hook:ProcessRBModule_FAR.
  Because switching SEL_XOR should be performed on RAM instead of ROM. 

Build 009: A02
- BIOS setup option for user to configure individual PCI Express ports in the
  MCH to behave as PCI Express v1.0 compliant since E7520 MCH B0 silicon are 
  PCI Express v1.0a compliant.
- Updated the CUSTCMOS from CUSTCMOS_00_00_13 to CUSTCMOS_00_00_14 to support
  read and write CMOS to GPNV during runtime.
- Updated the Intel Server management from ISM_00_00_82 to ISM_00_00_85.
- Updated the oemINT15 module from OEMINT15_00_00_22 to OEMINT15_00_00_26.
- Prevented the FRB3 to be disabled during bootblock.
- Implemented the Board SKU ID and update GPIO/PCI routing for hardware revision
  Fab4.
- Followed Board SKU ID to program Device SSID.
- Updated E7520 memory reference code v0.81
- Implemented the Rolling BIOS.
- Added Hub Interface & System Bus ERROR Handling Module to hardware engineer to
  debug.
- Implementeed the recovery function.
- Multi-Disk Recovery Feature supported.
- Updated Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache C-1 microcode to Revision 02.
- Killed lan stack before PCI optrom initializing.

Build 008: A01
- Supported SiI3124 RAID function.
- Enabled support for INT15h, Function DA20h, Subfunction 0786h: Write UUID.
- Implemented CPU_MCE_Handler_FAR for BIOS INT12h ISR.
- Implemented for SMBIOS type 30.
- Updated 6300ESB RAID option rom from 5.2.10281452 to 5.2.12011723.
- Maintained the DIMM failed LED after AC recovery.
- Updated LAN console from INTEL to fix track #15421 and #15422.
- Followed the "6300ESB Southbridge PCI Mode Performance Settings WhitePaper
  (December 2003)" to implement the PCI-X bridge(B0:D28:F0) performance setting
  for 6300ESB A3.
- BIOS workaround requested for MCH B0 support is regarding #2 in the E7520
  Sightings Report DDR 266 with an 800 MHz system bus non-functional in current
  MRC (Rev0.8)
- Fixed floppy controller disable cause system to hang up when detecting SATA 
  HDD.
- Bug fixed pressing <F2> will load CMOS default after resume from S4.
- Added BIOS SETUP items to "Chipset"->"MCH Configuration" menu for MCH B0 PCI-E
  port to choice programing PCI-E 1.0 Compliancy.
- Updated the following module from AMI remote source safe.
   (1) Updated 6300ESB eModule (ref. 8.00.10_SB-HRICH_007)
   (2) Updated E7520 eModule (ref. 8.00.10_NB-Lindenhurst_05)
   (3) Updated PCE-Express eModule (ref. 8.00.10_PCIE_03)
   (4) Updated Flash eModule from 8.00.00_FLASH-4MSTD64K_01 to
       8.00.00_FLASH-4MSTD64K_03.
   (5) Updated SMIFlash eModule from 8.00.00_SMIFlash-1.00.06 to
       8.00.00_SMIFlash-1.00.07.
   (6) Updated CPU eModule from 8.00.00_CPU-P4_3B.7 to 8.00.00_CPU-P4_3B.10.
   (7) Updated SMI - Module from 8.00.0_SMI-3.11.03 to 8.00.0_SMI-3.11.06.
   (8) Updated the USB module from 8.00.04_USB-2.23.01 to 8.00.04_USB-2.23.02.
   (9) Added Boot Block Vedio eModule 8.00.07_BBVideo-BETA-05_00.

Build 007: AC03
- Implemented the Single Norway option rom (v1.2.30 Beta-1).
- Implemented workaround for "Booting difficulties may be experienced when using
  certain PCI Express* cards." according to E7520/E7320/E7525 MCH BIOS update 
  v0.53.
- Updated ISM module from ISM_00_00_80 to ISM_00_00_82 and implement getting
  IP address from DHCP.
- Implemented the Hyper Threading enabled/disabled to BIOS setup menu.
- Bug fixed the incorrect device id of PCI-Express slot 4 since the device id
  is "0" instead of "5".
- Bug fixed welcome screen disappeared when installing RH Linux 8.0/9.0.
- Changed the BIOS Admin/User password to alphanumreic only.
- Implemented the FRB4 for HD/PXE boot.
- Bug fixed the SDR revision in BIOS setup menu.
- Bug fixed stack Corruption when booted to DOS with USB Keyboard & Console
  Redirection Enabled.
- Implemented PCI/PCI-X/PCI-Express VGA card as the top priority. 

Build 006: AC02
- Updated the AMI CORE from 8.00.09 to 8.00.10.
- Bug fixed the local keyboard malfunction when console redirection enabled.
- Updated the E7520 memory reference code from 0.75 to 0.80.
- Implemented the Intel Memory Test.
- Prevented the onboard NIC 82541GI 1Gb failed.
- Updated the 82541GI option rom from 1.12.16 to 1.12.17.
  Updated the SiI3124 option rom from 6003 to 6006.
- Implemented the RAID function for Hance Rapid.

Build 005: AC01
- Bug fixed the garbage message in the console redirection.
- Implemented the Save/Load Custom Defaults to BIOS setup menu.
- Implemented the Intel Diag LED.
- Implemented ECC event log.
- Bug fixed the EFI booting failed.
- Modified the Security in Bios Setup the same as Bios EPS 0.4.
- Implemented the INTEL OEM logo.
- Front Pannel (Power/Reset button) and NMI button Inhibited supported.
- Added CPU FSB 667MHz support.

Build 004: X04
- Bug fixes (ref. ISSUES FIXED section)
- Followed BIOS EPS 0.3 to implement BIOS SetupMenu.
- Updated BIOS module SB-HRICH_004 / PCIE_02 / USB2.23.01)
- Updated BIOS module ISM_00_00_77 / OEMINT15_00_00_21
- Enabled option ROM for Onboard SATA Sil3124
- Updated Memory reference code from v.70 to v.75
- Changed the KNI_DIS_N from SIO GPIO62 to GPIO51

Build 003: X03
- Bug fixed (ref. ISSUES FIXED section)
- SMBIOS function implemented.
- Serial COM2 function enabled.
- Implemented PCI ERR handling.
- Enabled memory Spread Spectrum

Build 002: X02
- Bug fixed (ref. ISSUES FIXED section)
- Serial Console Redirection ready for BIOS SetupMenu and DOS environment.
- ACPI SPCR feature ready for Windows 2003.

Build 001: X01
- Initial released.

=============================================================================
                                ISSUES FIXED
=============================================================================
Build 043: P.11
- N/A

Build 042: RC01.11
- WHQL Unreported Memory test will fail when PS2 devices are not connected.

Build 041: P.10
- N/A

Build 040: RC01.10
- Connecting USB keyboard but PS2 keyboard resulted in "Keyboard Nonfunctional" 
  event log, but there was keyboard connected to system.
- Least featured BSP change check failed.
- Pressing "F12" to boot from NIC, but it didn't follow the NIC prioriy in Boot 
  Device Priority in BIOS setup.
- BIOS tried booting from NIC device twice when pressing "F12" to boot from NIC.
- When populating Adaptec 29160 card and Nvidia Quadro 3400 card on SE7525GP2,
  it halted when 29160 self-test during POST.
- SMBIOS Type 20 got zero length for address space.
- Enabled all onboard devices with OpROM and populated LSI PCI RAID card with 
  HDD, BIOS displayed a POST error message "Insufficient memory to shadow PCI
  option ROM.

Build 039: P.09
- When MCH stepping more than C2, BIOS can't follow E7520_BSU_v1_07.pdf c
  larification #1 for recommended register settings.

Build 038: RC01_09
- Flow Control Settings in BIOS P08 Other Than RTS-CTS Cause Platform Hangs. 
- USB mouse not working on Intel RAID cards BIOS Console.
- SMBIOS Type 0 is not correct.
- SMDXREF test is failed.
- Serial can not work when onboard VGA is disabled.
- Intel(R) Xeon(R) 800MHz FSB/1M L2 Cache R-0 processor CPUID display issue 
  in BIOS SETUP.
- CPU frequency display different in the POST screen and BIOS setup with two 
  different frequency R0 stepping processors.

Build 037: P.08
-N/A

Build 036: RC02_08
- BIOS not implementing E7520 chipset errata #22 properly.
- BIOS logo status windows not displaying with custom logo
- nVidia graphics cards do not work on SE7525GP2. 
- Cert-WHQL-HCT12.1.01 Unreported Memory Test Fails on SKU3.
- Insufficient Memory to Shadow PCI ROM Message using nVidia QuadroFX3400 PCIE.
- Boot error with P07 BIOS w/ ATI or Nvidia cards & LSI SCSI.

Build 035: RC01_08
- 1GB physical memeory unavailable to WS2003 when 4GBs installed.
- SE7320SP2/SE7525GP2 UUID and CMOS statistics needed.
- Marvell Diagnostics hang with VP [MCH C4] 604MBs.
- Marvell Diagnostics v6.25 for Dual-Port NIC hangs on VP [C4] w.&w/o On-Brd NIC.
- Can't see HSC FW revision in BIOS.
- No error message for 2 CPUs with different frequency.
- Multiple Event Logs after MBE is generated.
- nVidia graphics cards do not work on SE7525GP2.

Build 034: P.07
-N/A

Build 033: RC01.07
- Support for 3 DIMM configuration? 
- Mellanox PIC-E card not initalizing properly.
- Cannot boot with Intel SRCU42X RAID card.
- There is no display during BIOS post when insert the MegaRAID SCSI 320-2X on 
  SE7525GP2.
- Special "HyperThread MPS" CMOS Token Required to Support FreeBSD.

Build 031: P.06
- N/A

Build 030: RC02.06
- Incorrect Processor Speed in SETUP, POST, SMBIOS and Windows  

Build 029: RC01.06
- System happened SERR and PERR when run WinPie stress test.  
- Parity error injection failure.
- [EFI] INT 0000006F, Unknown Interrupt ---Halt.
- SE7525GP2 BIOS fails to honor memory request from PTC 2-port PCIe Switch.
- AMCC 9xxx Adapter doesn't get it's BAR set properly.
- BIOS Int 15h issue.
- "PCI Onboard Unknown Device" displayed during POST.
             
Build 028: P05
- N/A

Build 027: RC04.05
- System hanged on stress test running/S4 test.
- System issued SERR when inserted Syskonnect SK-9E21D in PCI-E.

Build 026: RC03.05
- SATA drives periodically disappearing during reboots.

Build 025: RC02.05
- It happened blue screen when installed windows 2000 on Adaptec 39160.
- BIOS setup should support multi-language!
- System hanged on installation of Windows 2003 Server Enterprise.
- Some Setup items are missing in BIOS Setup Menu.
- System can't detect Intel-SRCU32U card when inserted in PCI 64 bits slot.
- Bootstrap Processor for Mixed Processor Steppping is not correct.
- Setup utility of Sil3124 was disappeared from time to time.
- Symantec Ghost 7.0 is not working properly.
- Type7 (Cache Information) of SMBIOS, Offset 05h (Cache Configuration) is not 
  correct.
- Red Water card plugged into X4 slot causes network and USB test to run slow.
- USB flash disk recovery boot doesn't work on all USB ports.
- 2nd CPU is not recognzed if Hyper Threading is disabled.
- USB Hotplug FD displays under CD/DVD Drives.
- SE7320SP2/SE7525GP2 BIOS:  Password mismatch errors cannot be cleared.
- 3Dlabs PCIe graphics adapter doesn't get its BARs initialized correctly.
- Multiple Event Logs after MBE is generated.
- Behavior on DBE injection in Non-RAS mode does not match EPS.
- Behavior on SBE injection in Non-RAS mode does not match EPS.
- "Memory Retest" Option in BIOS setup is not getting disabled after a reboot.
- Bus Uncorrectable Error occurred  in the process of WHQL11.2/ACPI stress test.
- Important sounding error in SEL does not give enough information to be useful.
- RedHat Linux kernel (Kernel : 2.4.21-15.EL) EM64T panic on shutdown.
- PCI-E correctable bus errors in slot 4.
- Windows enters ! if onboard video is not disabled.

Build 024: P04
- N/A

Build 023: P03
- MBE is not generating NMI
- Memory Multi-Bit Error is not logged.
- Memory Sparing doesn't work as Intel expected result

Build 022: P02
- N/A

Build 021: P01
- N/A

Build 020: RC01
- IBUAPI test failed.
- Support Type7 (Cache Information) of SMBIOS.
- Support Type7 (Cache Information) of SMBIOS.
- A password should be required for Floppy-Boot when secure mode boot is enabled
- Single memory should not support memory sparing.
- DMI TYPE11 is not updated correctly.
- Type11 OEM Strings not fully supported by SMBIOS.

Build 019: B02
- POST and Windows 2000 BIOS String do not match.
- When no valid RAID array is present, LSI OpROM forces user intervention.
- Mixed CPU Speeds are not supported correctly.
- Type17 (Memory Device) of SMBIOS is not set to 64bits.
- SMBIOS Type3 (System Enclosure or Chassis) does not support.
- Support Type17 (Memory Device) of SMBIOS not implimented.
- Type16 (Physical Memory Array) of SMBIOS not set to 8GB.
- Support for Type9 (System Slots) of SMBIOS.
- The String is too short in SMBIOS In Type 1~3.
- BIOS doesn't display"Keyboard Detected" on the POST Screen.
- SMBIOS Type19 (Memory Array Mapped Address) is not correct.
- Type20 (Memory Device Mapped Address) of SMBIOS is not correct.
- The Onboard VGA is not primary when Dual Monitor enabled.
- System will hang at POST if Nvidia PCI-E x16 card installed.

Build 018: B01
- Unable to disable PCI Option Rom.
- Wrong Error Message displayed when no memory is installed.
- Error Message for unsupported memory is incorrect per BIOS spec.
- CMOS checksum error will reset date/time.
- Some items in BIOS setup should be grayed out instead of hidden.

Build 017: BC08
- System  hung up when  LSI20160L is connected in PCI slot.
- System can't detect Intel-SRCU32U card when inserted in PCI 64 bits slot.
- IDE Boot will suspend when floppy controller is disabled.
- String Error during POST when Quick Boot is enabled.

Build 016: BC07
- **A20+ support for Himem.sys.
- System cannot boot form IDE channels unless disable Silicon3124 option Rom.
- Memory Information (Type 17 data in SMBIOS) is shown wrong.

Build 015: BC06
- Boot Option Command about booting form floppy is malfunction.
- Bios Lan console copyright is out of date .
- Changed the copyright string in the bottom of setup menu to 1985-2004.

Build 014: BC05
- System crashed at BIOS post when set BIOS second ATA channel to be S-ATA M-S.
- Set BIOS to be S-ATA M-S and install SuSE 9.0, the system crashed.

Build 013: BC04
- The incorrect information in the server management setup menu.
- Using USB 2.0 CD-ROM to install Win2000 SP4.

Build 012: BC03
- Protect the interrupt mask register to prevent system hang up at checkpoint
  3Ah.
- The incorrect DeviceSet of SMBIOS Type17.
- AVL Test fail (the same as #15767).
- Insert SCSI card 20160 to 64 bits pci slot and install SuSE 9.0, system 
  crashed.
- WHQL(11.2)-Unreported Memory and I/O Port test was failed under Windows.

Build 011: BC02
- Prevent BIOS to hang up at detecting 3th and 4rd IDE channel.
- The incorrect SVID/SSID because the SKU ID is incorrect.
- Multi-Bit error Event Log is not recorded!.
- MEMDAT failed in Real mode.
- Amidiag/Processor Test/Plug-n-Play Test Faileed on Fab4-D2D with Bios 2B00 
  because the flash part is locked.
- [ESC] cannot view diagnostic messages.
- Monitor Tach Fan 1, 2, 5, 6 failed.
- F1 key is ineffective to resume when system event log full.

Build 010: BC01
- N/A

Build 009: A02
- Event logging disable is not functional in BIOS setup.
- BIOS settings configuration/ wait for 'F1' if error disabled.
- SE7320SP2 only sees one of the onboard NICs.
- 3rd IDE and 4th IDE should not have both Master channel and slave channel.
- AC power cycling fail after 98 minutes.
- Run warm boot test is fail.
- ASR-2200S raid configuration utility can't be invoked.

Build 008: A01
- Install SuSE Linux 9.0 fail.
- SSU cannot read system event log.
- Event logging disable is not functional in BIOS setup.

Build 007: AC03
- W2k system will have a blue screen when PCI-E NICs are installed on slot4 and 
  6.
- Hard Disk OS boot time out in Bios Setup Utility doesn't work. 
- PXE Boot Timeout in Bios Setup Utility doesn't work.
- System hangs in Bios Setup Utility when PCI-E VGA is installed in PCI slot #6.
- "Stay On" and "Power Off" of FRB-4 policy in Bios Setup do not work. 
- Unreported Memory and I/O Port test of HCT 11.2 was failed.
- Password can have characters other than alphanumeric (a-z, A-Z, 0-9). 
- Welcome Screen Disappeared when installing RH Linux 8.0/9.0.
- PCI Compliance test of HCT 11.2 was failed.
- Hyper Threading Function did not disabled or enabled in BIOS setup menu.
- System will hang when 39160  plugged with HDD.
- PCI-VGA card is not the top priority when it is installed in PCI slot #3, #5. 

Build 006: AC02
- 1G onboard lan failed in BIOS 2A00.
- PXE boot failed in Bios 2A00.
- Keyboard fails to input when Bios Redirection Port is enabled in Bios 2A00. 

Build 005: AC01
- Serial Console Features Sub-menu Selection -- Testing Failed.
- System cannot load custom default.
- System doesn't request users to load defaut after CMOS is cleared.
- Security in Bios Setup is not corresponding to Bios EPS.
- Some items below Security in Bios Setup Utility should be hidden.
- Hot Key can't enforce system to enter Secure Mode.
- Redundant words after 3 consecutive incorrect password is entered.
- Post Code Changes after booting up to OS.
- Going into BIOS setup sometimes screen is blue and sometimes is gray.
- F8 fails to load failsafe default.
- Front Panel NMI button is malfunction.
- Power Switch Inhibit, Reset Switch Inhibit, NMI Control are not workable.

Build 004: X04
- System cannot install Windows XP Professional.
- COM2 doesn't work with Console Redirection.
- System cannot boot from floppy if S-ATA HDD was plugged.
- System doesn't halt during posting after CMOS data lost.
- system has no warning Beeps with no memory.
- The maximum length of password should be 7 characters.
- NO memory warning beeps.
- System cannot detect COM2.
- System hangs during posting.

Build 003: X03
- AMIDIAG 6.20 ACPI test failed.
- OEM Logo overlapped booting up screen.
- L1 and L3 cache size be detected as 0 KB.
- MPS Revision selecting item appeared on "MPS Configuration" and "SouthBridge 
  Configuration" at the same time .
- System hang up at post screen when BIOS scanning memory.

Build 002: X02
- DMA mode of SATA HDD was DMA-2 which detected by BIOS. 

Build 001: X01
- Intiial release.
	 
=============================================================================
                              REFERENCE MATERIAL
=============================================================================
Intel(R) Server Platform SE7320SP2 Technical Product Specification (TPS) 
Intel(R) WorkStation Platform SE7525GP2 Technical Product Specification (TPS) 

Technical Support: http://support.intel.com

[END OF RELEASE NOTES]