=============================================================================
Intel(R) Server Board SE7520JR2 BIOS RELEASE NOTES
=============================================================================
Intel Enterprise Platform & Services Marketing
Intel Corporation
2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA
=============================================================================
DATE:           September 29, 2006
TO:             Intel(R) server platform SE7520JR2 customers
SUBJECT:        BIOS Release Notes Production 12.10    (build 0092)
=============================================================================
Information in this document is provided in connection with Intel products 
and for the purpose of supporting Intel developed server boards and systems.
No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's
Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating
to fitness for a particular purpose, merchantability, or infringement of any
patent, copyright or other intellectual property right. Intel Corporation may
have patents or pending patent applications, trademarks, copyrights, or other
intellectual property rights that relate to the presented subject matter. The
furnishing of documents and other materials and information does not provide
any license, express or implied, by estoppel or otherwise, to any such
patents, trademarks, copyrights, or other intellectual property rights. Intel
products are not intended for use in medical, life saving, or life sustaining
applications. Intel may make changes to specifications and product
descriptions at any time, without notice.

Intel is a registered trademark of Intel Corporation.

*Other names and brands are the property of their respective owners.

Copyright (c) 2006 Intel Corporation.

=============================================================================
                              ABOUT THIS RELEASE
=============================================================================
Build #         : 0092
Build Stamp     : SE7520JR22.86B.P.12.10.0092.092920061139
Build Date      : September 29, 2006
Checksum        : 8C5C
=============================================================================
                           BIOS COMPONENTS/CONTENTS
=============================================================================
PXE Ver.        : Intel(R) Boot Agent GE v1.2.26, PXE 2.1 Build 083 (WfM 2.0)
SCSI Ver.       :(a) BIOS Versions:
			IM/IME BIOS  = 5.10.06
			IS BIOS  = 5.11.03
		 (b) FW version:
			FW versions with concatenated sEEPROM
			IM/IME  = 1.03.39
			IS  = 1.03.39
		sEEPROM  = Revision C

SATA Ver.       : ICH5R serial ATA RAID OPROM v5.4.10281401I.
VGA Ver.        : ATI* RAGE* XL GR-xlints3y.019-4.333
BIOS Base       : AMIBIOS 8.00.10

Processor stepping(s) supported: Intel(R) Xeon(TM) Processor 2.133MHz,
2.80GHz (with FSB 667MHz / 800MHz)

Microcode update versions:
F34h	17(M1DF3417) (Production) (D0)
F41h	17(MBDF4117) (Production) (E0)
F43h	05(M9DF4305) (Production) (N0)
F48h	0C(M01F480C) (Production) (A0)
F49h	03(MBDF4903) (Production) (G1)
F4Ah	02(M5DF4A02) (Production) (R0)

=============================================================================
                           SUPPORTED FUNCTIONALITY
=============================================================================
1.  6 * DIMMs DDR-266 / DDR-333 / DDRII-400
2.  Intel(R) Xeon(TM) Processor with 533MHz/667MHz/800MHz system bus speed.
3.  Multi-boot support.
4.  System Flash BIOS ROM
5.  COMA/COMB port
6.  CD-ROM boot
7.  Floppy port
8.  PCI 33/66, PCI-X 66/100/133 mode 1, PCI-E x 4, PCI-X 66/100/133 mode 2 slots
9.  ATI* Rage* XL VGA
10. Serial ATA Non-RAID
13. Clear CMOS
14. Legacy Power button
15. ACPI S0/S1/S4/S5
16. Setup screen
17. Legacy USB keyboard / mouse / Floppy / CDROM / HD
18. ARM (ATAPI Removable Media) / IRM (IDE Removable Media)
19. Custom CMOS save/restore
20. BIOS recovery
21. Multi-disk Recovery
22. Custom CMOS save/restore
23. Intel Platform Security
24. Intel Server Management
25. Custom CMOS backup/restore
26. IMT support
27. User Binary feature
28. SERR/MERR detection & logging for runtime
29. Int15 for ABS2.0
30. ACPI SPCR (Serial Port Console Redirection)
31. NMI detection for PERR/SERR
32. Rolling BIOS
33. SOL (Serial On Lan)


=============================================================================
                       SYSTEM FIRMWARE REQUIREMENTS/REVISIONS
=============================================================================
- PC87431M mini-Baseboard Management Controller (mBMC) from National Semiconductor:
  FW Revision 2.31 (or later)
- Intel(R) Management Module (IMM) BMC:
  FW Revision 0.20 (or later) *if IMM card installed
- SE7520JR2 FRU/SDR package:
  JR-6.2.1 (or later)

=============================================================================
             SYSTEM FIRMWARE REVISIONS TESTED AT TIME OF RELEASE
=============================================================================
- PC87431M mini-Baseboard Management Controller (mBMC) from National Semiconductor:
  FW Revision 2.40
- Intel(R) Management Module (IMM) BMC:
  FW Revision 0.52 *if IMM card installed
- SE7520JR2 FRU/SDR package:
  JR-6.7.1

=============================================================================
                           IMPORTANT INSTALLATION NOTES
=============================================================================
IMPORTANT NOTES:

(1) Floppy Update:
1. Extract Floppy.zip to a temporary folder.
2. Insert blank floppy diskette in drive A:
   **NOTE** : All Data on floppy diskette will be destroyed!
3. Run "MAKEFLPY.bat" to create two BIOS Update floppy diskettes.
4. Boot the system and press <F2> to run BIOS Setup.
5. For reference write down the current custom changes to any default settings 
   in the BIOS Setup program.  CMOS settings will be preserved across BIOS
   updates, but you may wish to use the "Save Custom Defaults" option on the 
   Exit tab to restore defaults later. Press <ESC> to exit BIOS Setup.
6. Boot system with Update Bios floppy.
7. When BIOS flash update is complete, it will display a message that all 
   writing and verification of flash is done.
   Next, power cycle the system.
8. If the FLASH process fails, please follow the BIOS Recovery Instructions 
   at the end of this document to recover the system BIOS.
9. Press <F2> to enter BIOS Setup, and verify the custom values you wrote 
   down in step 5 have been preserved.  If you used the "Save Custom Defaults"
   option, you can now "Load Custom Defaults".
   Press <F10> to save the values and exit Setup.
 

(2) Other bootable storage Update(size > 5MB):
Note: BOOT BLOCK changed, please run fbb.bat to update BIOS.
1. Extract BIOS.ZIP to a bootable storage such as USB DISK-ON-KEY. 
2. Boot the system and press <F2> to run BIOS Setup.
3. For reference Write down the current custom changes to any default settings 
   in the BIOS Setup program.  CMOS settings will be preserved across BIOS
   updates, but you may wish to use the "Save Custom Defaults" option on the 
   Exit tab to restore defaults later. Press <ESC> to exit BIOS Setup.
4. Place the bootable storage such as USB DISK-ON-KEY containing the new BIOS 
   into USB port of the system, and boot to pure DOS mode. (non-himem environment)
5. Run fbb.bat to update both system ROM and bootblock.
   **NOTE** : jumper J1A4 (BIOS partition selection) should be set to 
   pins 1-2 to select the correct BIOS partition.
6. Please use the latest distributed tools (fbb.bat/afudos.exe)
   to update BIOS.
   Command "fbb.bat" will program main BIOS & bootblock.
7. When BIOS flash update is complete, it will display a message that all 
   writing and verification of flash is done.
   Next, power cycle the system.
8. If the FLASH process fails, please follow the BIOS Recovery Instructions
   at the end of this document to recover the system BIOS.
9. Press <F2> to enter BIOS Setup, and verify the custom values you wrote 
   down in step 3 have been preserved.  If you used the "Save Custom Defaults"
   option, you can now "Load Custom Defaults".
   Press <F10> to save the values and exit Setup.


=============================================================================
                            KNOWN ISSUES/WORKAROUNDS
=============================================================================
- The BIOS setup item "Maximum CPUID Value Limit" must be enabled for 
  installing some legacy OSes which do not support it.
- For NT4.0 installation, user must manually to disable legacy USB & enable 
  "Maximum CPUID Value Limit" from BIOS setup.
- USB KB/MS works abnormal in NT4.0 after BIOS P.09.00.
=============================================================================
                             FEATURES ADDED
=============================================================================
Build 0092: P.12.10	
- None.

Build 0091: P.12.00	
- None.

Build 0090: RC01.12.00	
- Exposing BMC resources via ACPI.

Build 0089: P.11.00	
- None.

Build 0088: RC01.11.00	
- None.

Build 0087: P.10.00	
- None.

Build 0086: RC02.10.00	
- None.

Build 0085: RC01.10.00	
- Include microcode for G-1 stepping.
- Add the codes for handling of mixed VID max voltage CPUs.
  1. 0199 error: Processor voltage mismatch detected in mixed stepping configuration. (Halt)
  2. 019A error: Processor voltage mismatch detected.(Pause)
- Support IPMI get platform Information command.
- Display OEM sign On message from SMBIOS Type 1 Manufacturer sting when this string is not Intel.
- Put the SMBIOS Type 11 OEM string to memory F000:E840h.

Build 0084: P.09.10	
- Include microcode for A-0 stepping of Dual-Core Intel(R) Xeon(TM) Processor with 2x 2 MB L2 Cache.

Build 0083: P.09.00	
- None.

Build 0082: RC01.09.00	
- Support Dual-Core Intel(R) Xeon(TM) Processor on JR-2 new baseboard.
- Add new microcode 
  1. F34 - M1DF3417.pdb(Production rev 17) Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 1 MB L2 Cache, D-0 stepping.
  2. F43 - MBDF4117.pdb(Production rev 17) Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 1 MB L2 Cache, E-0 stepping.
  3  F41 - M9DF4305.pdb(Production rev 05) Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 2 MB L2 Cache, N-0 stepping.
  3. F48 - M5FF4807.pdb(Production Candidate rev 07) Dual-Core Intel(R) Xeon(TM) Processor with 2x 2 MB L2 Cache, A-0 stepping.
  4. F49 - MBDF4903.pdb(Production Candidate rev 03) Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 1 MB L2 Cache, G-1 stepping.
  5. F4A - M5DF4A02.PDB(Production Candidate rev 02) Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 2 MB L2 Cache, R-0 stepping.
- Add to issue 5 beep code for installing one Dual-Core Intel(R) Xeon(TM) Processor into un-supported board.
- Add a setup sub-menu for "Power Management Feature" to control wake on LAN from S5.

Build 0081: P.08.10	
- (none)

Build 0080: P.08.00	
- (none)

Build 0079: RC03.08.00
- (none)

Build 0078: RC02.08.00
- (none)

Build 0077: RC01.08.00
- Add a setup option to clear Eventlog automatic when it is full.
- Add to support Mixed CPU configuration error message(0198).
- Add a new setup option to actually disable the logging of the Timestamp Sync.
  event(0x83) that happens every boot.
- Add to generates 3 beeps when total memory ranks more then MCH limit.


Build 0076: P.07.40
- (none)

Build 0075: P.07.30
- (none)

Build 0074: P.07.20
- (none)

Build 0073: P.07.10
- (none)

Build 0072: P.07.00
- (none)

Build 0071: RC02.07.00
- Include Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 1 MB L2 Cache, E-0 stepping Production microcode M9DF4112

Build 0070: RC01.07.00
- Upgrade DOSCMOS module to 00_00_05 revision.
- Set recommended register setting(program D8:F0:R4Ch bits[13:0] to 0) by MCH BIOS Spec Update v1.03
- Update Rolling BIOS module to Beta 8 revision.
- Update LSI SCSI OpROM for Integrated Striping (IS) mode to v5.11.02.
- Update IST module to 8.00.10_IST_11B.
- Add another code to support loop back testing with different jumper setting.
- Update ISM module to revision 00_01_03.

Build 0069: P.06.00
- (none)

Build 0068: RC01.06.00
- Add MCH Errata 31: MCH responds with illegal access on the Hub interface for 32 GB memory configurations.
- Add MCH Errata 32: Memory reference code not recognizing Address/Command parity capable ECC DIMMs.
- Update IST module to 8.00.10_IST_11
- Update micro code by Int15 failed when ILFBSP swap BSP to AP.
- Update CPU module to 8.00.00_CPU-P4_3C.08.
- Add CPU microcode M9DF4304.txt to support N-0 stepping of Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 2 MB L2 Cache.
    	 Microcode update versions:
         F43h    04(M9DF4304) (Production Candidate) (N0)
- Update CPU D-0 and E-0 micro code.
	F34h	14(M1DF3414) (Production Candidate) (D0)
	F41h	0D(MBDF410D) (Production Candidate) (E0)
- Add to support toggle Quiet Boot splash screen when a OpROM is executing in the background.
- Add to support IPMI command for don't pause when POST error occur.
- Add to support clear custom CMOS defaults when the clear CMOS by user.
- Disable Adjacent Cache Line Prefetch and Hardware Prefetcher per the Processor BWG v0.9

Build 0067: P.05.00
- (none)

Build 0066: RC02.05
- Add to switch MUX to system before performing any serial port initialization.

Build 0065: RC01.05
- Update CPU module to 8.00.00_CPU-P4_3C.07.
- Upgrade Intel Least Feature BSP module to 8.00.07_ILFBSP_03. 
- Upgrade Rolling BIOS module to Beta5. 
- Update IBA v1.2.26 
- Update cache descriptor table(CPUID function 2). (CPUP40053)
- Switch MUX to system before SIO init.
- Include Set ACPI Power state command to IMM from Intel.

Build 0064: P.04.40
- (none)

Build 0063: P.04.30
- (none)


Build 0061: P.04.00
- (none)

Build 0060: RC01.04.00
- Add PCI-E ACPI MCFG table.
- Move some code from RUN_CSEG to SMBIOS_CSEG to increase runtime space.
- Add AMI CORE_m037 from Intel John to fix for the second part of the 
  issue regarding errors reading AMIBOOT.ROM.
- H/W request v022 for register setting. cfg (0,6,0)[3Eh]<1> = 1b
  	 cfg (0,7,0)[3Eh]<1> = 1b
         cfg (0,6,0)[6Ch]<3> = 0b
         cfg (0,7,0)[6Ch]<3> = 0b
         cfg (0,6,0)[14Ch]<20> = 1b
         cfg (0,7,0)[14Ch]<20> = 1b
- Add CPU microcode MBDF4109(Production) for Intel(R) Xeon(TM) Processor E-0 stepping

Build 0059: P.03.00
- (none)

Build 0057: RC03.03.00
- Add AMI CORE_m037 from Intel John to fix USB flash drive doesn't work in bootblock.
- Remove not production CPU microcode.

Build 0056: B20.03
- Add Required Register Settings per MCH BSU 0.82, document#64:To take full advantage 
  of the changes in the MCH Silicon, for stability on MCH B0 stepping and above, 
  Intel recommends that BIOS clear bit 12 of D0:F2:R0A4h and set   bit 15 of D0:F2:R09Ch 
  very early during boot.
- Add H/W request v016 for register setting:
     	1. change cfg (0,0,1)[64h]<5> to 1b from 0b.
	2. change cfg (0,2,0)[3Eh]<1,0> to 00b from 11b.
- Remove the NEC MWA support for E7520 in code per Intel request. Intel side state that it can 
  fix defect where system hangs during POST if OOB connection has been established.
- Upgrade u-code to M1DF3413.TXT (Production Candidate) for Intel(R) Xeon(TM) Processor D0.
- Update Intel Least Feature BSP source code from Intel.
	1. Change description: ID CORE_m031_r01
	   solve that issue hang at option ROM initialization if swap BSP to LFP.
		. related file                   BSP\eM\ILFBP\ILFBP.ASM        
        2. Bootstrap Processor for Mixed Processor Stepping is not correct.
	3. Change description: ID CORE_m031
		Update AMI TAG CORE0114 (Wed 07-14-2004)
  		If system have two or more processor were matched least feature, BIOS 
                will check CPU signature then promote oldest processor to BSP.
- Add H/W request v021 for register setting.	
	1. Change cfg (0,2,0)[3Eh]<1> to 1b from 0b.
	2. Change cfg (0,2,0)[14Ch]<20> to 1b from 0b.

Build 0055: B19.03
- Update to IBA v1.2.22.
- Add to support Clear CMOS by BMC when IMM installed.

Build 0054: B18.03
- ensure at least 1.5 sec delay before access PCI configuration space.
- Add BIOS setup item [Main -> Server Board MCH Stepping -> Stepping] to show MCH revsion.

Build 0053: B17.03
- Update DOS CMOS e-module to DOSCMOS_00_00_03.
- Update CPU module to 8.00.00_CPU-P4_3C.06.
- Add an EFI-32 Welcome Screen message from Intel displayed just before the 
  EFI Shell prompt appears.
- Add support INT15 DA12 from Intel John.

Build 0053: P.02.00
- Remove not production yet cpu microcode.

Build 0052: B16.02
- Make "Floppy A" disabled and grayed out when "Onboard Floppy Controller" 
  was disabled in BIOS setup.

Build 0050: P.01.00
- Add display Non-Fatal or Fatal for PCI-E uncorrectable error NMI.
- Change to not recovery NCBLK 0 & 1.
- Do retry if SMBUS error.
- Add to set the Memory Sparing item to disable during POST when the previous 
  boot is not support Sparing.
- Set ACPI mode Configuration command (C0h/83h) to the BMC to update the ACPI 
  mode bit when the ACPI mode changes.
- Remove board information "SE7520JR2 2 SCSI for fab3 or later" for BIOS P.01.0 
  during POST.
- Remove not yet production CPU microcode. SE7520JR2 BIOS P.01.00 will only have 
  the microcode M1DF340E.TXT for Intel(R) Xeon(TM) Processor,
  so it will only support Intel(R) Xeon(TM) Processor D0 stepping (CPU Id F34).

=============================================================================
                              ISSUES FIXED
=============================================================================
Build 0092: P.12.10
- Fix system hangs with active riser.

Build 0091: P.12.00
- None.

Build 0090: RC01.12.00
- Un-hiding the "Remote Console Reset" setup option and utilizing it to support the <ESC> R <ESC> r <ESC> R sequence to reboot in Serial Console.
- Fix NMI can't be targeted when disabling "ECC Event Logging" on BIOS Setup.
- Clear PERR/SERR status bit when system got PCI-E error.
- Update Paxville DP CPU microcode to revision 0C.

Build 0089: P.11.00
- Update LSI SCSI IME OpROM to v5.10.06 without BETA message.

Build 0088: RC01.11.00
- Fix SBE error will log wrong DIMM number to BMC under symmetric mode.
- Fix USB mouse can not work in NT4.0 when Port 60/64 emulation is enabled.
- Set ACPI S4 power state to IMM when system goes to hibernate.
- Inclued AMI fix CORE0014 to fix DMA mode in SETUP was disappeared sometimes.
- Chnage the NMI default value to enable for IMM.
- Update platform ID in ACPI OEMRSDT string for Jarrell-2 to 7520JR23, Jarrell-1 to 7520JR22.

Build 0087: P.10.00
- None.

Build 0086: RC02.10.00
- Upgrade ICH5R serial ATA RAID OPROM to v5.4.10281401I.
- Fix Lan1/2 of SMBIOS structure type 8 are different with Silkscreen.

Build 0085: RC01.10.00
- Do not set the legacy "SERR Enable" bit and instead use the PCI-E specific bits in the"Device Control Register"
  to control PCIE error erporting: Set the "Non-Fatal" and "Fatal Error Reporting Enable" bits, but not the 
  "Unsupported request Reporting Enable".
- Per MCH errata 22 to set root port(0/2/0,0/6/0) register 45h bit3 to disable Completion timeout Timer.
- Per MCH BSU v1.07 to set PAM to un-cacheable.
- Fix PCI-E correctable error event log still log the 11th error.
- Change to disable and gray out "Assert NMI on PERR" when "Assert NMI on SERR" is disabled.
- Fix when console redirection is enabled and LSI20320R is installed, insufficient PCI ROM space error reports
  even if disabling ROM for LSI20320R.
- Fix PCI-E error injection causes the root port receiver(114h bit0) error be masked.
- Fix ASR2230SLP/256MB OpROM will not be initialized.
- Fix Secure Mode Boot does not prompt for password before boot.
- Fix CMOS checksum bad and custom default loaded when saving custom CMOS twice and reset system.
- Per HW recommended register setting 0.27 to set EXP_MASKERR 144-147h bit 0-2 to 1.
- Fix particular case when in some CPU combination the processor's feature flag values in the system do not 
  match with the least feature flag values.
- Fix BIOS didn't set legacy mode to BMC when shutdown from ACPI mode.
- Fix when Serial Redirection is enabled, DC000~DD800h can not allocate to another OpROM shadow.
- Workaround Abnormal SEL log Event #31 with D0 stepping CPU.
- Wordaround System can not boot with GE Medical VRAC card.
- Wordaround System can not enter ASC-48300 SAS card option ROM utility.
- Include the missing code of AMI CORE0155.
- Inclue AMI bug fix 2341 to fix garbage characters displayed for the POST message when
  it should instead say "Tape Drive" for the Tape drive detected.
- Fix SMBIOS shows wrong I2C slave Address
- Fix can not boot to Red Hat Linux 9 kernel 2.4.20-8smp with one CPU HT on.
- Change the setup item "Serial Port Connector" visible only when "BIOS Redirection Port" is disabled and
  "ACPI Redirection" is enabled.

Build 0084: P.09.10
- Fix to Set the Echo TPR Disable bit for R-0 stepping Intel(R) Xeon(TM) Processor with 800 MHz 
  System Bus and 1 MB L2 Cache & A-0 stepping Dual-Core Intel(R) Xeon(TM) Processor.
- Fix can't boot with Dual-Core Intel(R) Xeon(TM) Processor after battery off.
- Fix CPU count for Dual-Core Intel(R) Xeon(TM) Processor on POST Display and BIOS Setup.
- Update CPU string with "Dual-Core" text on POST Display for Dual-Core Intel(R) Xeon(TM) Processor
  and remove "with EM64T".

Build 0083: P.09.00
- Remove A-0 microcode for Dual-Core Intel(R) Xeon(TM) Processor with 2x 2 MB L2 Cache.
- Remove G-1 microcode for Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 1 MB L2 Cache.
- Revert to the previous version of EXEC.C as in P.08.00.

Build 0082: RC01.09.00
- Fix Serial console can not work when VGA is disabled.
- Update ISM module to ISM_00_01_05.
- Following PXH BIOS spec 1.03 section 4.1.2 to set the IOAPIC disable.
- Fix the PCI-SIG test cases 1.1.
- Programming PXH(1/0/0,1/0/2) register 130h bit7,8,9,11 and 12 to 0.
- Setting MCH root port Max Payload size to 256B(6Ch bit 5-7)and Max read Request size to 512B to increase PCI-E performance.
- Fix USB keyboard works abnormal after INT19 when port 60/64 emulation is enabled.
- Fix system hang after AC loss when Install 3.8 GHz N-0 stepping of Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 1 MB L2 Cache.
- Fix String(BIOS Vendor) spelling wrong in SMBIOS type 0.
- Add a CPU error exception from Intel for inserting D0 and G1 stepping.
- Add to check the additional 128-bit Extended Feature Flag information for the Lowest-Feature Processor detection algorithm.
- Following PXH BSU 1.04 to set the PXH(F0/F2) register 184h bit 2 to 1.
- Fix GRNB menu auto booting not working when exit from EFI-32 Shell.

Build 0081: P.08.10
- Update EFI32 to WW20.2 and Uhchlp.c(WW21.1) to fix EFI works abnormal when loop back installed in COM A.
- Fix Intel SpeedStep Technology works abnormally.

Build 0080: P.08.00
- (none)

Build 0079: RC03.08.00	
- Clear USB 2.0 PCI register 6Ch bit 1 and bit 14.
- Fix System can not detect PCI error.
- Fix installed 6*DIMM and configured RAS to Mirroring, there are
  exhibited the wrong memory states after poisoned in Bank2.
- Fix Update Type 17 Bank locator.
- Modify to update DIMM status immediately in BIOS setup once the Memory
  RAS state is configured for mirroring or sparing.
- Fix IMM will turn on DIMM failed LED when it controls Fan FRU LED.
- Update Load.c of EFI e-Module.
- Change the Intel Speed Step default value to disable for fixing W2k3/Sp1 S1 issue.

Build 0078: RC02.08.00	
- Force non-compliant nVidia graphics card to use 32bit addressing.
- Include CPU e-Module fix CPU40059 to fix IMT memory test too slow.
- Add a workaround to fix Several RAID cards will hang at IRQ6 when POST.
- Fix SBE can not be logged in SEL.
- Fix can't light faulty DIMM LED even if SBE counter exceeds its threshold.
- Update Ehci.c of EFI e-Module to fix Console Redirection no longer work in EFI.

Build 0077: RC01.08.00	
- Fix Fault LED and Wrong Message can not indicate the Bad Memory
  Bank on POST in SBE.
- Fix System can not report 8170 error.
- Upgrade Rolling BIOS e-Module to Beta9 revision.
- Fix Wrong Memory status under BIOS setup when total memory rank
  in 8 and under Mirror mode.
- Fix Memory Spare not supported when bank0 larger then bank1 and 2.
- Remove the entries for EISA ID ports.
- Fix FRB4 policy only work at the 1st time but failed at 2nd time or later.
- Fix Set Power & reset button inhibit to "enabled", user still can
  perform CMOS clear via Front Panel when DC off.
- Update setup string (Memory RAS) with Multi-language.
- Fix Boot selection does not present all USB devices.
- Upgrade USB e-Module to 2.24.00_Beta5.
- Add BMC selftest retry to get the BMC status.
- Downgrade IST e-Module back to IST_09A.
- Upgrade EFI module to WW15.3.
- Fix memory sizing error may destroy CP.
- Fix Network boot option only probes first NIC only.
- Fix System reports "Insufficient Memory to Shadow PCI ROM" when
  installed LSI 21320 SCSI card.
- Fix asserting NMI on PERR/SERR works abnormal during POST time.
- Fix System can not shut-down when 3COM Modem Card "USR5610B" 
  populated in any slots.
- Fix System won't boot with some cards(2 or more PXSA4 Adapters,
  Write Cache add-in card) installed.
- Fix PCI-SIG PCI-E test suite failed.
- Fix Multiple EventLog for SBE and MBE.
- Fix User Binary Mask20 can not be executed if "No Runtime Code" bit is set in
  the structure.
- Update LSI SCSI BIOS & FW.
  IM/IME BIOS  = 5.10.04
  IS BIOS  = 5.11.03
  FW = 1.03.39

Build 0076: P.07.40
- Fix IMM is not getting valid video when we have double termination and bad common
  biasing on the DVI interface.

Build 0075: P.07.30
- Fix Windows Server 2003 with /PAE dose not see 16GBs (4x4GB DIMMs).
- Upgrade ATI VGA OpROM (GR-xlints3y.019-4.333).

Build 0074: P.07.20
- Add a BIOS workaround to fix LSI 320-2 FW1L33 OpROM issue.

Build 0073: P.07.10
- BMC timestamp fix.
- CPU setup option changes.
  1. Modify some CPU setup option strings.
  2. Set default of "Intel(R) Speed Step(TM) Tech" to Auto.
  3. Set default of "Execute Disable Bit" to Enable.
  4. Make "Hardware Prefetcher and Adjacent Cache Line Prefetch"
     options available as specified and default value is disabled.
- Fix for very slow booting if KVM is enabled.
- Fix for SetSystemBootOptions command will not keep previous setting.

Build 0072: P.07.00
- (none)

Build 0071: RC02.07.00
- Include some help text corrections omitted from RC01.07 
- Fix defect introduced by USER Flash side-effect in RC01.07 
- Fix for Int13h, function 15h 
- Fix for SCSI OpROM issue with console redirection enabled 
- Fix for PMM cannot find enough extended memory for <F2> setup menu after OpROM 
- Fix for updating SMBIOS Type 1/2/3 default string and Chassis Manufacturer field.

Build 0070: RC01.07.00
- Change the default value of Enhanced Halt State(Q_C1E_SUPPORT) to enabled per Intel request.
- Change the Rolling BIOS error codes from 88XX to 86XX to match EPS1.05.
- Fix pressing "ESC" to toggle Quiet Boot splash screen when a OpROM is executing in the background
  will also skip OpROM init if the OpROM utility supports ""ESC"" to skip OpROM init."
- Set recommended register setting(program D8:F0:R4Ch bits[13:0] to 0) by MCH BIOS Spec Update v1.03.
- Fix User Binary execution issue.
- Fix when clearing Admin Password not clearing User Password.
- Fix customer requires new BIOS setup option for special handling of HTT CPU 
  for FreeBSD v4.5 compatibility.
- Remove the code relate with GPNV event logging to reduce code size.
- Including AMI Core Fixes USB0062 and USB0090 to support 1GB USB DOK.
- Use AMI Tools17 and NEWPATCH.EXE v1.03 instead of AMI Tools15 to build RC01.07.
- Modify the Memory RAS feature per Intel request.
- Modify some strings to match EPS v1.05.
- Fix Hot Swap FAN Fault LED turning on unexpectedly in Riggins LX Chassis
- Fix PXE Boot NIC order is incorrect
- Fix BIOS can not detect ELPIDA 1G DDR2 DIMM.

Build 0069: P.06.00
- Change CPU microcode status as following:
	M1DF3414.TXT | Assembly format, Revision 14 | D-0 (Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 1 MB L2 Cache)   
	MBDF410D.TXT | Assembly format, Revision 0D | E-0 (Intel(R) Xeon(TM) Processor with 800 MHz System Bus and 1 MB L2 Cache)  
  remove N0 non-production microcode.

Build 0068: RC01.06.00
- Fix the OPROM utility console will destroy by press <ESC> and <F12>.
- Fix DMIEDIT update smbios type 11 failed.
- Fix update micro code for any other stepping not present in NCBLK2 will destroy previous micro code.
- Fix can not enter OPROM utility console of Adaptec Series SCSI/SATA Raid card.
- Fix system hang when trying to enter OPROM utility console of AAR-1210SA and AAR2410SA.
- Fix BIOS does not log SBE correctly.
- Add AMI errata #20040001: CMOS checksum will fail after 30~40 times reboot.
- Fix full load storage stress failed under RHEL AS 3.0 U3 32 bit OS.
- Include AMI fix for connecting USB stick scrambles boot order.
- Fix [F2] BIOS Setup Hot Key not recognized thru console redirection over LAN

Build 0067: P.05.00
- (none)

Build 0066: RC02.05
- Take back out the mirroring setup option.
- Fix PXE-E04, PXE-E05 error.

Build 0065: RC01.05
- Fix Show "In-sufficient Memory to Shadow PCI ROM" at POST ending if system "Enabled" onboard SCSI 
  and S-ATA RAID at the same time.
- Fix Cursor jumping at POST ending point if Emulation "enabled"
- Fix USB 2.0 not supported by current EFI drivers.
- Fix PCI card memory space address is allocated above 4GB 
- Fix Addressing Adapters in 64-bit Environment
- Fix Power & Reset Button still been locked when Clear Password Jumper 1-2 is closed.
- Fix power restore policy as the following cases.
	Target: mBMC 2.40. Restore policy: Always off.
	Pull off AC power cord when the target system is power on.
	Pull on AC power cord again after about 10 seconds.
	The target system is turn on but this action is not an expected action.
	Result : Fail
- Fix Jarrell BIOS B17 does not recognize the option rom on OEM HPPQS board.
- Fix Power/Reset Button would be locked if the selection of Power/Reset switch Inhibit on BIOS Setup 
  is "Enabled" with graying.
- Fix Incorrect SDR version being displayed in Bios Server Management page.
- Fix floppy controller resource always exist if floppy controller disabled by auto detect floppy present.
- Fix update micro code fail form Int15.
- Fix Memory Fault DIMM LED's are not ON after injecting the SBE 10th in Non RAS mode
- Fix CMOS would be cleared after pressing ESC key on remote site several times.
- Fix SetSystemBootOptions to have console redirection on next boot not overriding bios configuration
- Fix Int15, Function E801h can not report correct memory size when installed 3GB memory in system
- Fix BIOS SMI code will disable both MBE & SBE detection when SBE is over 10 times in an hour.
- Fix when an option ROM hooks INT19h to gain control at boot and the user has entered and exited 
  the BBS popup without selecting a boot device, the option ROM does not regain control.
- Fix timing issue with display toggle cause Logo corruption.
- Add back the Memory mirroring setup option.
- Remove disable SIO WDT at SIO init and include some loss (RBF0010) of upgrade RB module Beta4 revision.
- Move procedure PIC_WORKAROUND_FAR to POST_CSEG from RUN_CSEG to free more space in segment RUN_CSEG.
- Setup question updates for BWG 0.9's requirement.  (CPUP40054)
	1.Change setup question "Adjacent Cache Line Prefetch" and "Hardware Prefetcher" poweron 
          and default value to "Enabled".
	2.Change the wording of NX function(change to "Execute Disable bit")
- Change _STR$_Intel_SpeedStep_tech from "Intel@ Speed Step tm Tech" to "Intel(R) Speed Step(TM) Tech".
- Remove check NVRAM layout checksum before save/load custom default.
- Change to AMITOOLS 17. use AMISSP2.EXE "-t" parameter in CORE.MAK

Build 0064: P.04.40
- Fix BIOS will show "Clear CMOS by jumper" and keep clear CMOS until AC off when clear CMOS by IMM.

Build 0063: P.04.30
- Fix BIOS POST hang during DC power cycling tests. 
  That is add syncSMBUS command to IMM.
- Fix Super IO Config Option removed from P04 BIOS. 
  That is add back Super IO Config Options (BMC mode selection).

Build 0061: P.04.00
- Fix the system hang during the POST time if BSP "disabled". 
- Fix the system hang during the POST time if AP swapped.
- Fix System hung at memory count after several reset processes on P03.00
- Fix Memory RAS: Actual failover is not reported after injecting multi-bit error
- Fix BAR error on PCI-E card which behind MCH C0 port.

Build 0060: RC01.04.00
- Fix Memory Fault LED's are not sticky on system reboot in Memory Sparing.
- Fix BIOS detects a Floppy Drive even when a Floppy Drive is not present.
- Fix from Intel RB Patch.
- Fix POST show "Clear CMOS by jumper" when clear by IMM
- Fix if main bios micro code module has the last micro and load from main bios 
  will cause system hang at 20.
- Fix RC03.03 recovery fail from legacy floppy.
- Fix can not toggle to another bank if BIOS hang between D1 with 78.
- Fix sometimes system hang at memory count. (maybe)
- Fix sometimes will occur FSB mismatch error when installed E-0 stepping CPU.
- Fix Spelling error in oemboard.asd.
- Fix E820 table will report error if disabled remap and installed 4G memory.
- Fix BIOS is not enabling FW access to the FRU LED. 
- Fix SMBIOS type 19 show incorrect end address when sparing mode.
- Fix BIOS setup item "NMI Control" no function when IMM is present. 
- Fix if AP is the least feature, the SMBIOS Type 4 CPU2 information will disappear.

Build 0059: P.03.00
- Add a display item in setup to show MCH stepping. and fix BIOS REPORTS MCH4 as D0.
- Add implementation of MCH BSU 0.82 Errata#73 for MCH IRQ hang workaround when MCH 
  stepping is "C2" or earlier.
- Change USB2.0 dedicate to use IRQ5 instead of IRQ7 due to MCH PIC mode workaround 
  use IRQ7 for LINKA/B/C/D.
- Fix System does not blue screen when injected with multi-bit error.
- Fix SE7520JR2 BIOS help text for PCI Priority Arbitration Setting.

Build 0057: RC03.03.00
- Fix SOL issue, update SOL.ASM from Intel.

Build 0056: B20.03
- Fix PCIe error not behaving as expected.
- Fix Setup menu display CPU2 status wrong if CPU2 disabled by BMC.
- Fix Incorrect CPU information on SMBIOS Type4 if BSP was disabled.
- Fix "Front Side bus mismatch" displayed if Processor 01 disabled.
- Fix modify the Memory Maximum Capacity on SMBIOS Type 16 to "Dynamic".
- Fix always load micro code from NCBLK 2 during POST if NCBLK has micro code.
- Fixed system reset when booting from PC DOS J6.30/V bootable CD with Acer 
  CD-ROM 36X/AKU CDROM drive.
- Fixed When IDE and COM port share the same IRQ, system hangs in DOS with the 
  message "Stack overflow".
- Fix Some legacy scsi BIOS + windows bootable CD will cause FDD access failure. 
  Example: Tekram scsi BIOS.
- Fix Multi-Disk Recovery feature sometimes fail on TEAC USB Floppy.

Build 0055: B19.03
- Fix recovery fail form USB Plextor CD-RW.
- Fix System can't shutdown correctly under RHEL AS3 U2 64 bits.
- Fix Display wrong BIOS version on Win2k.
- Fix SMBIOS type 19 will show incorrect value when sparing mode enabled.
- Fix BIOS setup item "NX Support" has been hidden on NX supported CPU.
- Fix The Hot Key message is disorderly on OEM Splash Screen when output by 
  G450 add-in card.
- Fix some SMBIOS data were wrong on JR2 MLB.
- Fix Unable to auto power off NetWare 6.5 SP1 server, when inserted 
  LP9002LP-F2 card into Full Length PCI-X Slot.

Build 0054: B18.03
- Change the Socket Designation information indicate as CPU 1/CPU 2 instead of 
  CPU 0/CPU 1 in SMBIOS Type 4.
- Fix BIOS report wrong CPU information if Processor 1 disabled.
- Fix Can't not detect presence of single DIMM when IMM installed.
- Fix PCI-E Unsupported Request Mask register not enabled.
- Fix USB ports fail high speed black box testing
- Remove Free 8K(E000~E2000) of E000 segment for option ROM shadow. 
  This will fix issues bellow:
    1 BIOS hangs after SCSI option ROM init.
    2 Fix system can not boot when ZCR card installed.- 

Build 0053: B17.03
- Fix the boot order may become scrambled when a new device is introduced to the 
  "Boot Device Priority" menu in BIOS setup.
- Free 8K(E000~E2000) of E000 segment for option ROM shadow. 
- Fix recovery mode will destroy some RB Flag.
- Remove the BIOS setup item [Advanced -> SuperIO Configuration -> Serial Port Mode]& 
  [Advanced -> SuperIO Configuration -> SIM Tri-State].
- Fix use AFUDOS /ixx.rom /kx fail.

Build 0053: P.02.00
- (N/A)

Build 0052: B16.02
- Add the code that AMI modify for Boot Block USB CD-Rom recovery from Intel John.
- Fix it always display the <F2> message in Quite boot mode even 
  if the "Hit <F2> Message Display" is disable in setup menu. Show strings 
  "Press <F12> for Network Boot" if the "Hit <F2> Message Display" is disabled.
- Fix USB High Speed J, K test (DC spec) exceeds specification -all ports
- Fix Memory Fault LED's not glowing on memory sparing.
- Add displaying Sparing DIMMs information per slot in BIOS setup.
- Remove u-code M0DF3308 due to there was no C-0 stepping (F33) Intel(R) Xeon(TM) Processor.
- Change the BIOS POST message "IA32e Capability" as "EM64T".

Build 0050: P.01.00
- Fix For MCH C1 or later, PCI-E Error displayed at POST and system hung 
  if "Empty" PCI-E riser existed.
- Fix BINIT# not logged to SEL.
- Fix the CPU BIST(MSR 2A bit1) will be disabled after warm boot or press 
  reset button.
- Remove Mirror string in setup menu for SRA not support Mirror.
- Fix some words of the help string of "Max CPUID Value Limit" in 
  [Advanced|Processor Configuration] disappeared.
- Fix use 64-bit PCI instead of MMIO code.
- Review multi-language string follow ASD_07072004.zip & NEW_07092004.asd
- Fix error code (0146) occur will display wrong color if bus or dev 
  number over 10.
- Fix onboard SCSI option ROM disable cause the LSI-20320 not init option 
  ROM on SCSI board.
- Fix Mirroring feature not present in the BIOS setup menu (Mirroring Not 
  supported on BIOS Ver B13)
- Fix Platform Mismatch communication between BIOS and BMC (IMM). 
       	1. Send SE7520JR2 Platform id 01 to BMC.
		(1) Early in POST (just after memory initialization, when we have 
		    a stack) the BIOS will communicate a unique numeric platform ID 
		    code to the BMC using Intel OEM command 0Fh. 
		(2) After it, the BMC will check to see if the firmware matches the 
		    indicated platform type. If a mismatch occurs, the BMC will log 
		    a self test error code of C5h, 00h and log an event to the SEL. 
		    The sensor type of this event will be 2Bh, version change, offset 03h, 
                    "firmware incompatibility detected".
		(3) When a mismatch is detected, the BMC will reconfigure the LM93 
		    PWMs inverted/non-inverted output control(s) to match the actual 
		    platform fans. Note that this requires that this a-priori fan 
		    knowledge be built into the firmware.
	2. Check if Platform mismatch.
		(1) Near the end of POST, BIOS will check for a platform mismatch, 
		    again using OEM command 0Fh. If a mismatch is indicated, BIOS 
		    will display a warning message on the CRT. Current wording of the 
		    platform mismatch error message is : 
	            "Intel(R) Management Module firmware and FRUSDR update required" .  
	            This error message should be a warning only, not a pause.
- Fix WHQL-HCT 11.2 unreported Memory and IO Port test failed when plugging IMM under W2K3.
- Fix Can't detect Processor 2 when enforce FRUSDR utility.
- Modify the error message "Thermal Trip failure" to "Thermal failure due to PROCHOT#" 
  to avoid confuse to user.
- Fix booting to disk on key with XP format Fat32 will cause hang.
- Change core.mak for Freeze the "CMOS" map for RC cause the LastCmosStorage of 
  toktbl2.asm and ssp.rep are different from before. These changes also cause 
  some warning message in build.log.
- Workaround LP10000DC 3x FC storage adapter throughput is slot dependent on 
  2U LP and FL passive risers. From Intel Ritchie's request for. Add a option 
  under PCI configuration setup in BIOS with something like: PCI priority arbitration 
  enable/disable. This would be disabled by default and would only be enabled for if 
  someone was using certain cards and seeing the throughput issue. Add a BIOS setup 
  item [Advanced -> PCI Configuration -> PCI Priority Arbitration] with options 
  "Disabled/Enabled", and its default is disabled.

=============================================================================
                              REFERENCE MATERIAL
=============================================================================
Intel(R) Server Board SE7520JR2 BIOS External Product Specification (EPS)
Intel(R) Server Board SE7520JR2 Technical Product Specification (TPS)

=============================================================================
                        BIOS RECOVERY INSTRUCTIONS
=============================================================================
    **NOTE** : - If running recovery, jumper J1A4 (BIOS partition selection) should set to 
                 pins 1-2 to select the correct BIOS partition.
               - The recovery only supports the storages of both type 12 & FAT16.

- Build Recovery Storage
  A.Recovery from Big Storage
  	1.    Prepare a formatted storage such as USB DISK_ON_KEY.
  	2.    Copy AMIBOOT.ROM to it.
  B.Multi-Disk Recovery
  	1.    Prepare 2 blank disks.
  	2.    Copy amiboot.000 to disk0, amiboot.001 to disk1.
- Execute BIOS Recovery
  1.    User Forced Recovery
        - set Recovery Boot Jumper J1H2 (2-3)
        - Attach the recovery storage. (plug USB-DISK-ON-KEY or insert disk0...)
        - Power on system
        - System boot and start recovery operation.
        - During multi-disk recovery operation, system will beep for once (1sec) continuously 
          to notice user insert disk1 (which contains amiboot.001)
        - When flash complete, system will beep 4 times and follow an endless beep, 
          set jumper back to Normal mode J1H2 (1-2) and power off system.
        - Recovery operation complete.
  2.  Auto Recovery
        - If system ROM is damaged (checksum BAD), system will perform BIOS
          recovery automatically.

- Note:- When BIOS get into RECOVERY MODE, the screen doesn't have any response 
  due to rolling-bios limitation. 
 (continuous 5 short beep means recovery fail, 4 short beep and then a long endless 
  beep means recovery successful.)

=============================================================================
  
[END OF RELEASE NOTES]
