;	TITLE	BMP.bsf - BMP Scrip File for Video BIOS
;==============================================================================
; Advance Graphics ROM BIOS
;------------------------------------------------------------------------------
; Copyright (c) Intel Corporation (2000 - 2003).
;
; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS
; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT,
; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES.
; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS.
; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY,
; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER
; WARRANTY.
;
; Intel disclaims all liability, including liability for infringement of
; any proprietary rights, relating to use of the code. No license, express
; or implied, by estoppel or otherwise, to any intellectual property rights
; is granted herein.
;
; File Description:
;	This file is the script file use by the BMP utility which will allow
;	OEM's to edit data and select features on a binary file.
;
;------------------------------------------------------------------------------


;==============================================================================
; Header - Start of BMP Structure Definition
;------------------------------------------------------------------------------

StructDef

Find			"BIOS_DATA_BLOCK "

			; The following block will determine the reference
			; pointer for all table pointer variables.

Find_Ptr_Ref		"BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data

$BDB_Ver		2 bytes		; BIOS Data Block version number (decimal, e.g.201 = 02.01) 
$BDB_Header_Size	2 bytes		; BIOS Data Block Header size
$BDB_Size		2 bytes		; BIOS Data Block size 


;==============================================================================
; Block 254 - Signon Strings and Other General Data
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$Bmp_BIOS_Size		2 bytes
$BIOS_Type		1 byte		; BIOS Type:
					; = 0, DESKTOP
					; = 1, MOBILE

$RelStage		1 byte		; Release status

$Chipset		1 byte		; = 0 - Almador
					; = 1 - Brookdale-G
					; = 2 - Pineview
					; = 3 - Springdale-G
					; = 4 - Grantsdale-G
					; = 5 - Alviso
					; = 6 - Copper River
					; = 7 - Lakeport
					; = 8 - Calistoga
					; = 9 - Broadwater-G
					; = 10 - Crestline
					; = 11 - Poulsbo
					; = 12 - Bearlake-B
					; = 13 - Cantiga
					; = 14 - EagleLake

$Integrated_LVDS	1 bit		; Integrated LVDS Support:
					; 1 = Yes
					; 0 = None

$Integrated_TV		1 bit		; Integrated TV Support:
					; 1 = Yes
					; 0 = None
					
$Integrated_EFP	1 bit		; Integrated EFP Support:
					; 1 = Yes
					; 0 = None

$eDP			1 bit		; eDP:
					; 1 = Yes
					; 0 = None

SKIP			4 bits
SKIP			4 bytes		; Skip build number string

			; Signon and copyright strings

$Signon			155 bytes	; Signon string
SKIP			61 bytes	; Copyright string

			; General Byte Definitions

$bmp_BIOS_CS		2 bytes		; BIOS code segment
$bmp_DOS_Boot_Mode	1 byte		; Mode number to set when DOS is boot
$bmp_BW_Percent		1 byte		; Set percentage of total memory BW
SKIP			1 byte		; Popup Memory Size
$bmp_Resize_PCI_BIOS	1 byte		; BIOS size granularity in 0.5 KB
SKIP			1 byte		; Is the CRT already switched to DDC2

$Allow_Boot_DVI		1 bit		; Allow boot DVI even not attach
$Allow_Aspect_Ratio	1 bit		; VBIOS aspect ratio for DOS
SKIP			6 bits

ALIGN

;==============================================================================
; Block 1 - General Bit Definitions
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

			; bmp_Bits_1

$Enable_Panel_Fitting	2 bits		; Enable / Disable panel fitting
$Flexaim_Support	1 bit		; Enable / Disable Flex-aim support
$Msg_Enable		1 bit		; Disable signon and copyright
$Cls_After_Signon	3 bits		; Clear screen after display message and pause
$bmp_DVO_A_Color_Flip	1 bit		; Flat color flip
ALIGN

			; bmp_Bits_2
$Download_Ext_VBT 	1 bit		; Download external VBT flag
$Enable_SSC		1 bit		; Enable/Disable SSC
$SSC_Freq		1 bit		; SSC Frequency
$Enable_LFPOn_Override	1 bit		; Enable/Disable LFP ON Override
$Disable_SSC_DDT	1 bit		; Disable SSC in Dual Display Twin
$Override_VGA_720p	1 bit		; Enable/Disable Override 720p for VGA modes
SKIP			2 bits
ALIGN

			; bmp_Bits_3
			
$Disable_Smooth_Vision	1 bit		; Disable smooth vision
$Single_DVI_I		1 bit		; Single DVI-I connector for CRT and DVI display
SKIP	 		6 bits
ALIGN

$bmp_Legacy_Monitor_Detect  1 bit	; Use legacy monitor detect algorithm
SKIP			7 bits
ALIGN

			; Int_Displays_Support

$Int_CRT_Support	1 bit		; Integrated CRT support
$Int_TV_Support	1 bit		; Integrated TV support
$Int_EFP_Support	1 bit		; Integrated EFP support
$DP_SSC_Enb		1 bit		; DP SSC Enable bit
$DP_SSC_Freq		1 bit		; DP SSC Frequency bit
SKIP			3 bits

      #IF	($BIOS_Type == 1 && $Chipset == 8) || ($BIOS_Type == 0 && $Chipset == 7)
      					; Mobile && ( CAL or CRL ) || Desktop && LP_G
SKIP			4 bytes		; Build number echo for driver
      #ENDIF	; ($BIOS_Type == 1 && $Chipset == 8) || ($BIOS_Type == 0 && $Chipset == 7)
ALIGN


;==============================================================================
; Block 254 - PRD Boot Algorithm Table
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			32 bytes	; Skip PRD boot algorithm table


;==============================================================================
; Block 2 - General Data Definitions
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

			; bmp_DDC_GPIO_Pins

$CRT_DDC_GMBUS_Pin	1 byte		; CRT DDC GMBUS pin pair

			; bmp_DPMS_Bits

$DPMS_ACPI_Bit		1 bit		; Apply ACPI DPMS CRT Power States
$Skip_Boot_CRT_Detect	1 bit		; Disable/Enable skip boot CRT detect
$DPMS_AIM_Bit		1 bit		; Apply DPMS to AIM devices
SKIP			5 bits
ALIGN

			; bmp_Boot_Dev_Bits

$Boot_Display		2 bytes		; Boot display type

$size_ChildStruc	1 byte

			; Internal TV Data structure

      #IF	$Integrated_TV == 1	; $Integrated_TV == TRUE
SKIP			33 bytes	; Skip TV data structure
      #ENDIF	; $Integrated_TV == TRUE

			; Internal LVDS Data structure

      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
SKIP			19 bytes	; Skip data structure
$LFP_DDC_GMBUS_Pin	1 byte		; LFP DDC GMBUS pin pair
SKIP			13 bytes
      #ENDIF	; $Integrated_LVDS == TRUE

			; Internal EFP (HDMI/DP) Data structure

      #IF	$Integrated_EFP == 1	; $Integrated_EFP == TRUE
SKIP			2 bytes		; Skip Device Handle
$Int_EFP1_Type		2 bytes		; Device type
SKIP			12 bytes	; Skip
$Int_EFP1_Port		1 byte		; EFP1 port
SKIP			2 bytes		; Skip
$Int_EFP1_DDC_Pin	1 byte		; EFP1 DDC Pin
SKIP			3 bytes
$Int_EFP1_Docked_Port	1 byte		; HDMI/DP Docked Port
$Int_EFP1_HDMI_Compat	1 bit		; HDMI combatibility
$Int_EFP1_Conn_Info	3 bits		; Connector information
SKIP			4 bits
$Int_EFP1_AUX_Channel	1 byte		; DP AUX channel
SKIP			7 bytes		; Skip

SKIP			2 bytes		; Skip Device Handle
$Int_EFP2_Type		2 bytes		; Device type
SKIP			12 bytes	; Skip
$Int_EFP2_Port		1 byte		; EFP1 port
SKIP			2 bytes		; Skip
$Int_EFP2_DDC_Pin	1 byte		; EFP1 DDC Pin
SKIP			3 bytes
$Int_EFP2_Docked_Port	1 byte		; HDMI/DP Docked Port
$Int_EFP2_HDMI_Compat	1 bit		; HDMI combatibility
$Int_EFP2_Conn_Info	3 bits		; Connector information
SKIP			4 bits
$Int_EFP2_AUX_Channel	1 byte		; DP AUX channel
SKIP			7 bytes		; Skip
      #ENDIF	; $Integrated_EFP == TRUE

SKIP			33 bytes	; Skip device data structure
SKIP			33 bytes	; Skip device data structure
SKIP			33 bytes	; Skip device data structure
SKIP			33 bytes	; Skip device data structure

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
;==============================================================================
; Block 3 - Original Display Toggle List
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$bmp_Display_Detect	1 byte		; Display must be attached or not
      #ENDIF	; $BIOS_Type == MOBILE


;==============================================================================
; Block 4 - Mode Support Bit Definitions
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			28 bytes	; Mode List


;==============================================================================
; Block 254 - Hook Defintions
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
$H31_POST_End_Hook	1 byte		; POST end hook int vector
$H33_After_Mode_Set	1 byte		; After mode set hook
$H35_Bootup_Display	1 byte		; Bootup display hook
$H38_Before_Mode_Set	1 byte		; Before mode set hook
$H45_VESA_DDC_Hook	1 byte		; VESA DDC hook interrupt vector
$H46_VESA_PM_Hook	1 byte		; VESA PM hook interrupt vector
$H47_Notify_Display_Sw	1 byte		; Notify display switch hook
$H48_After_VESA_PM	1 byte		; After VESA PM hook
$H14_Update_Display	1 byte		; Update Expansion/Display State Hook
$H14_Get_Misc_Status	1 byte		; Get Miscellaneous Status Hook
$H36_Boot_TV_Format	1 byte		; Boot TV to NTSC/PAL
$H34_Set_LFP_Fitting	1 byte		; Set panel fitting flags
$H40_Set_Panel_Type	1 byte		; Set panel fitting flags
$H49_Get_BL_Inv_Pol     1 byte		; Get inverter type and polarity for backlight
      #ELSE	; $BIOS_Type == MOBILE
$H35_Bootup_Display	1 byte		; Bootup display hook
$H36_Boot_TV_Format	1 byte		; Boot TV to NTSC/PAL
$H34_Set_LFP_Fitting	1 byte		; Set panel fitting flags
$H40_Set_Panel_Type	1 byte		; Set panel fitting flags
      #ENDIF	; $BIOS_Type == MOBILE

			; BMP - Pointer tables

$Dev_Boot_Table_Ptr	2 bytes		; Start at BMP Boot table
$Dev_Boot_Table_Size	2 bytes
$Dev_Boot_Table,	$Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
$Dev_Removed_Table_Ptr	2 bytes		; Start at BMP Remove configurations table
$Dev_Removed_Table_Size	2 bytes
$Dev_Removed_Table,	$Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte
      #ENDIF	; $BIOS_Type == MOBILE

$MMIO_Boot_Table_Ptr	2 bytes		; Start at BMP Boot table
$MMIO_Boot_Table_Size	2 bytes
$MMIO_Boot_Table,	$MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte

$SWF_IO_Table_Ptr	2 bytes
$SWF_IO_Table_Size	2 bytes
$SWF_IO_Table,		$SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes

$SWF_MMIO_Table_Ptr	2 bytes
$SWF_MMIO_Table_Size	2 bytes
$SWF_MMIO_Table,	$SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes


$Mode_Rem_Table_Ptr	2 bytes		; Start at BMP Boot table
$Mode_Rem_Table_Size	2 bytes
$Mode_Rem_Table,	$Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
$Toggle_List1_Ptr	2 bytes		; Start at BMP Boot table
$Toggle_List1_Size	2 bytes
$Toggle_List1,		$Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte

$Toggle_List2_Ptr	2 bytes		; Start at BMP Boot table
$Toggle_List2_Size	2 bytes
$Toggle_List2,		$Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte

$Toggle_List3_Ptr	2 bytes		; Start at BMP Boot table
$Toggle_List3_Size	2 bytes
$Toggle_List3,		$Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte

$Toggle_List4_Ptr	2 bytes		; Start at BMP Boot table
$Toggle_List4_Size	2 bytes
$Toggle_List4,		$Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte
      #ENDIF	; $BIOS_Type == MOBILE

$ScalarCoeff_Tab_Ptr	2 bytes
$ScalarCoeff_Tab_Size	2 bytes
$ScalarCoeff_Tab,	$ScalarCoeff_Tab_Ptr, $ScalarCoeff_Tab_Size, Offset 0 bytes

$LFP_DTD_01_Ptr		2 bytes
$LFP_DTD_01_Size	2 bytes
$LFP_DTD_01,		$LFP_DTD_01_Ptr, $LFP_DTD_01_Size, Offset 0 bytes
$LFP_DTD_02_Ptr		2 bytes
$LFP_DTD_02_Size	2 bytes
$LFP_DTD_02,		$LFP_DTD_02_Ptr, $LFP_DTD_02_Size, Offset 0 bytes
$LFP_DTD_03_Ptr		2 bytes
$LFP_DTD_03_Size	2 bytes
$LFP_DTD_03,		$LFP_DTD_03_Ptr, $LFP_DTD_03_Size, Offset 0 bytes
$LFP_DTD_04_Ptr		2 bytes
$LFP_DTD_04_Size	2 bytes
$LFP_DTD_04,		$LFP_DTD_04_Ptr, $LFP_DTD_04_Size, Offset 0 bytes

$LFP_PID_01_Ptr		2 bytes
$LFP_PID_01_Size	2 bytes
$LFP_PID_01,		$LFP_PID_01_Ptr, $LFP_PID_01_Size, Offset 0 bytes
$LFP_PID_02_Ptr		2 bytes
$LFP_PID_02_Size	2 bytes
$LFP_PID_02,		$LFP_PID_02_Ptr, $LFP_PID_02_Size, Offset 0 bytes
$LFP_PID_03_Ptr		2 bytes
$LFP_PID_03_Size	2 bytes
$LFP_PID_03,		$LFP_PID_03_Ptr, $LFP_PID_03_Size, Offset 0 bytes
$LFP_PID_04_Ptr		2 bytes
$LFP_PID_04_Size	2 bytes
$LFP_PID_04,		$LFP_PID_04_Ptr, $LFP_PID_04_Size, Offset 0 bytes

$LFP_Pwr_Seq_01_Ptr	2 bytes
$LFP_Pwr_Seq_01_Size	2 bytes
$LFP_Pwr_Seq_01,	$LFP_Pwr_Seq_01_Ptr, $LFP_Pwr_Seq_01_Size, Offset 0 bytes
$LFP_Pwr_Seq_02_Ptr	2 bytes
$LFP_Pwr_Seq_02_Size	2 bytes
$LFP_Pwr_Seq_02,	$LFP_Pwr_Seq_02_Ptr, $LFP_Pwr_Seq_02_Size, Offset 0 bytes
$LFP_Pwr_Seq_03_Ptr	2 bytes
$LFP_Pwr_Seq_03_Size	2 bytes
$LFP_Pwr_Seq_03,	$LFP_Pwr_Seq_03_Ptr, $LFP_Pwr_Seq_03_Size, Offset 0 bytes
$LFP_Pwr_Seq_04_Ptr	2 bytes
$LFP_Pwr_Seq_04_Size	2 bytes
$LFP_Pwr_Seq_04,	$LFP_Pwr_Seq_04_Ptr, $LFP_Pwr_Seq_04_Size, Offset 0 bytes

      #IF	$eDP == 1		; $eDP == TRUE
$eDP_Pwr_Seq_01_Ptr	2 bytes
$eDP_Pwr_Seq_01_Size	2 bytes
$eDP_Pwr_Seq_01,	$eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes
$eDP_Pwr_Seq_02_Ptr	2 bytes
$eDP_Pwr_Seq_02_Size	2 bytes
$eDP_Pwr_Seq_02,	$eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes
$eDP_Pwr_Seq_03_Ptr	2 bytes
$eDP_Pwr_Seq_03_Size	2 bytes
$eDP_Pwr_Seq_03,	$eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes
$eDP_Pwr_Seq_04_Ptr	2 bytes
$eDP_Pwr_Seq_04_Size	2 bytes
$eDP_Pwr_Seq_04,	$eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes
$eDP_Pwr_Seq_05_Ptr	2 bytes
$eDP_Pwr_Seq_05_Size	2 bytes
$eDP_Pwr_Seq_05,	$eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes
$eDP_Pwr_Seq_06_Ptr	2 bytes
$eDP_Pwr_Seq_06_Size	2 bytes
$eDP_Pwr_Seq_06,	$eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes
$eDP_Pwr_Seq_07_Ptr	2 bytes
$eDP_Pwr_Seq_07_Size	2 bytes
$eDP_Pwr_Seq_07,	$eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes
$eDP_Pwr_Seq_08_Ptr	2 bytes
$eDP_Pwr_Seq_08_Size	2 bytes
$eDP_Pwr_Seq_08,	$eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes
$eDP_Pwr_Seq_09_Ptr	2 bytes
$eDP_Pwr_Seq_09_Size	2 bytes
$eDP_Pwr_Seq_09,	$eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes
$eDP_Pwr_Seq_10_Ptr	2 bytes
$eDP_Pwr_Seq_10_Size	2 bytes
$eDP_Pwr_Seq_10,	$eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes
$eDP_Pwr_Seq_11_Ptr	2 bytes
$eDP_Pwr_Seq_11_Size	2 bytes
$eDP_Pwr_Seq_11,	$eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes
$eDP_Pwr_Seq_12_Ptr	2 bytes
$eDP_Pwr_Seq_12_Size	2 bytes
$eDP_Pwr_Seq_12,	$eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes
$eDP_Pwr_Seq_13_Ptr	2 bytes
$eDP_Pwr_Seq_13_Size	2 bytes
$eDP_Pwr_Seq_13,	$eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes
$eDP_Pwr_Seq_14_Ptr	2 bytes
$eDP_Pwr_Seq_14_Size	2 bytes
$eDP_Pwr_Seq_14,	$eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes
$eDP_Pwr_Seq_15_Ptr	2 bytes
$eDP_Pwr_Seq_15_Size	2 bytes
$eDP_Pwr_Seq_15,	$eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes
$eDP_Pwr_Seq_16_Ptr	2 bytes
$eDP_Pwr_Seq_16_Size	2 bytes
$eDP_Pwr_Seq_16,	$eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes
      #ENDIF	; $eDP == 1		; $eDP == TRUE

;==============================================================================
; Block 6 - Extended MMIO Register tables
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

      #IF	$Chipset == 4		; $Chipset == GD-G
SKIP			357 bytes	; Skip data
      #ELSEIF	$Chipset == 5		; $Chipset == ALVISO
SKIP			365 bytes	; Skip data
      #ELSEIF	$Chipset == 7		; $Chipset == LP-G
SKIP			357 bytes	; Skip data
      #ELSEIF	$Chipset == 8		; $Chipset == CAL 
SKIP			365 bytes	; Skip data
      #ELSEIF	$Chipset == 9		; $Chipset == BW-G
SKIP			421 bytes	; Skip data
      #ELSEIF	$Chipset == 10		; $Chipset == CRL
SKIP			413 bytes	; Skip data
      #ELSEIF	$Chipset == 11		; $Chipset == PSB
SKIP			365 bytes	; Skip data
      #ELSEIF	$Chipset == 12		; $Chipset == BL-B
SKIP			357 bytes	; Skip data
      #ELSEIF	$Chipset == 13		; $Chipset == CTG
SKIP			397 bytes	; Skip data
      #ELSEIF	$Chipset == 14		; $Chipset == ELK
SKIP			397 bytes	; Skip data
      #ELSEIF	$Chipset == 2		; $Chipset == PNV
SKIP			373 bytes	; Skip data
      #ENDIF	; $Chipset


;==============================================================================
; Block 7 - IO Software flag register table for initializaton
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			7 bytes		; Skip data


;==============================================================================
; Block 8 - MMIO Software flag register table for initializaton
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			61 bytes	; Skip data


      #IF	$Chipset == 0		; $Chipset == ALMADOR
;==============================================================================
; Block 9 - Dot Clock Table.
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			264 bytes	; Skip data
      #ENDIF	; $Chipset == ALMADOR


;==============================================================================
; Block 10 - Modes Removal Table.
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
SKIP			203 bytes	; Skip data
      #ELSE	; $BIOS_Type == MOBILE
SKIP			163 bytes	; Skip data
      #ENDIF	; $BIOS_Type == MOBILE


;==============================================================================
; Block 11 - Child Device Configuration Table.
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			1 byte		; Child structure size

			; Generic device 1 data structure

SKIP			2 bytes		; Skip Device Handle
$Dev1_Type		2 bytes		; Device type
$Dev1_I2CSpeed	1 bytes		; I2C speed used to communicate to codec
SKIP			9 bytes		; Skip Reserved_1
SKIP			2 bytes		; Skip AddInOffset
$Dev1_DVO		1 byte		; DVO port
$Dev1_I2C_Pin		1 byte		; I2C GPIO pin pair
$Dev1_Slave_Add		1 byte		; I2C slave address
$Dev1_DDC_Pin		1 byte		; DDC GPIO pin pair
SKIP			2 bytes		; EDID Buffer Ptr
$Dev1_DVO_Cfg		1 byte		; DVO Port config
$Dev1_Sec_DVO		1 byte		; DVO port
$Dev1_Sec_I2C_Pin	1 byte		; Secondary I2C GPIO pin pair
$Dev1_Sec_Slave_Add	1 byte		; Secondary I2C slave address
$Dev1_Sec_DDC_Pin	1 byte		; Secondary DDC GPIO pin pair
SKIP			1 byte		; Capabilities
$Dev1_DVOWiring		1 byte		; DVO Wiring
$Dev1_Sec_DVOWiring	1 byte		; DVO Wiring for secondary device
$Dev1_Type_Ex		2 bytes		; Extended device class
$Dev1_DVO_Func		1 byte		; DVO function

			; Generic device 2 data structure

SKIP			2 bytes		; Skip Device Handle
$Dev2_Type		2 bytes		; Device type
$Dev2_I2CSpeed	1 bytes		; I2C speed used to communicate to codec
SKIP			9 bytes		; Skip Reserved_1
SKIP			2 bytes		; Skip AddInOffset
$Dev2_DVO		1 byte		; DVO port
$Dev2_I2C_Pin		1 byte		; I2C GPIO pin pair
$Dev2_Slave_Add		1 byte		; I2C slave address
$Dev2_DDC_Pin		1 byte		; DDC GPIO pin pair
SKIP			2 bytes		; EDID Buffer Ptr
$Dev2_DVO_Cfg		1 byte		; DVO Port config
$Dev2_Sec_DVO		1 byte		; Secondary DVO port
$Dev2_Sec_I2C_Pin	1 byte		; Secondary I2C GPIO pin pair
$Dev2_Sec_Slave_Add	1 byte		; Secondary I2C slave address
$Dev2_Sec_DDC_Pin	1 byte		; Secondary DDC GPIO pin pair
SKIP			1 byte		; Capabilities
$Dev2_DVOWiring		1 byte		; DVO Wiring
$Dev2_Sec_DVOWiring	1 byte		; DVO Wiring for secondary device
$Dev2_Type_Ex		2 bytes		; Extended device class
$Dev2_DVO_Func		1 byte		; DVO function

			; Generic device 3 data structure

SKIP			2 bytes		; Skip Device Handle
$Dev3_Type		2 bytes		; Device type
$Dev3_I2CSpeed	1 bytes		; I2C speed used to communicate to codec
SKIP			9 bytes		; Skip Reserved_1
SKIP			2 bytes		; Skip AddInOffset
$Dev3_DVO		1 byte		; DVO port
$Dev3_I2C_Pin		1 byte		; I2C GPIO pin pair
$Dev3_Slave_Add		1 byte		; I2C slave address
$Dev3_DDC_Pin		1 byte		; DDC GPIO pin pair
SKIP			2 bytes		; EDID Buffer Ptr
$Dev3_DVO_Cfg		1 byte		; DVO Port config
$Dev3_Sec_DVO		1 byte		; Secondary DVO port
$Dev3_Sec_I2C_Pin	1 byte		; Secondary I2C GPIO pin pair
$Dev3_Sec_Slave_Add	1 byte		; Secondary I2C slave address
$Dev3_Sec_DDC_Pin	1 byte		; Secondary DDC GPIO pin pair
SKIP			1 byte		; Capabilities
$Dev3_DVOWiring		1 byte		; DVO Wiring
$Dev3_Sec_DVOWiring	1 byte		; DVO Wiring for secondary device
$Dev3_Type_Ex		2 bytes		; Extended device class
$Dev3_DVO_Func		1 byte		; DVO function

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE

			; Generic device 4 data structure

SKIP			2 bytes		; Skip Device Handle
$Dev4_Type		2 bytes		; Device type
$Dev4_I2CSpeed	1 bytes		; I2C speed used to communicate to codec
SKIP			9 bytes		; Skip Reserved_1
SKIP			2 bytes		; Skip AddInOffset
$Dev4_DVO		1 byte		; DVO port
$Dev4_I2C_Pin		1 byte		; I2C GPIO pin pair
$Dev4_Slave_Add		1 byte		; I2C slave address
$Dev4_DDC_Pin		1 byte		; DDC GPIO pin pair
SKIP			2 bytes		; EDID Buffer Ptr
$Dev4_DVO_Cfg		1 byte		; DVO Port config
$Dev4_Sec_DVO		1 byte		; Secondary DVO port
$Dev4_Sec_I2C_Pin	1 byte		; Secondary I2C GPIO pin pair
$Dev4_Sec_Slave_Add	1 byte		; Secondary I2C slave address
$Dev4_Sec_DDC_Pin	1 byte		; Secondary DDC GPIO pin pair
SKIP			1 byte		; Capabilities
$Dev4_DVOWiring		1 byte		; DVO Wiring
$Dev4_Sec_DVOWiring	1 byte		; DVO Wiring for secondary device
$Dev4_Type_Ex		2 bytes		; Extended device class
$Dev4_DVO_Func		1 byte		; DVO function

      #ENDIF	; $BIOS_Type == MOBILE

			; ADD-Card SPD as device #6 and #7
			; They should be non-BMPable

SKIP			66 bytes	; Skip two data structures


;==============================================================================
; Block 12 - Driver default boot display
;------------------------------------------------------------------------------

SKIP		   	3 bytes		; Skip block ID and size
$Driver_Boot_Device	1 bit
$Block_Disp_Switch	1 bit
$Allow_FDOS_Disp_Switch 1 bit		; Allow FS DOS display switching
$Hot_Plug_DVO		1 bit
$Dual_View_Zoom		1 bit
$Drv_Int15_hook		1 bit
$DVD_Sprite_Clone	1 bit
$Use_110h_for_LFP	1 bit 
ALIGN

$Driver_Boot_Mode_X	2 bytes		; X resolution
$Driver_Boot_Mode_Y	2 bytes		; Y resolution
$Driver_Boot_Mode_BPP 	1 byte		; Pixel depth
$Driver_Boot_Mode_RR  	1 byte		; Refresh rate

$Enable_LFP_Primary	1 bit
$GTF_Mode_Pruning	1 bit
     #IF	$Chipset == 13 || $Chipset == 10 || $Chipset == 8
     					; $Chipset == (CTG || CRL || CAL)
SKIP			1 bit		; DISABLE_DFGT
SKIP			1 bit		; DISABLE_DFGT
     #ELSE	; $Chipset == 13 || $Chipset == 10 || $Chipset == 8
$Render_Freq_Switch	1 bit
$Render_Freq_Default	1 bit 
     #ENDIF	; $Chipset == 13 || $Chipset == 10 || $Chipset == 8
$NT4_Dual_Dsp_Clone_Spt 1 bit		; Dual display clone support for NT4
$Default_Power_Scheme	1 bit
$Sprite_Display_Assign	1 bit		; Sprite Display Assignment for When
					; Overlay is Active in Clone Mode
$CUI_Maintain_Aspect	1 bit		; Display "Maintain Aspect Ratio" via CUI
$Preserve_Aspect_Ratio	1 bit		; Preserve Aspect Ratio
$SDVO_Device_Power_Down	1 bit		; SDVO device power down
$Hot_Plug_CRT		1 bit		; CRT hot plug
$LVDS_Config		2 bits		; LVDS configuration
$Hot_Plug_TV		1 bit		; Hot plug TV enable/disable
$INT_HDMI_Config	2 bits		; Integrated HDMI Configuration
ALIGN

$CUIHotK_Static_Display	1 bit
SKIP		   	7 bits
$Legacy_Monitor_Max_X	2 bytes
$Legacy_Monitor_Max_Y	2 bytes
$Legacy_Monitor_Max_RR	1 bytes
ALIGN

$Enable_Int_Src_Term	1 bit		; Enable Internal Source Termination for HDMI
SKIP		   	7 bits
ALIGN

$VBT_Customization_Version 1 byte	; Customization VBT version number
ALIGN

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
;==============================================================================
; Block 13 - Driver Persistence Algorithm
;------------------------------------------------------------------------------

SKIP			  	3 bytes		; Skip block ID and size

$Driver_Persist_Hotkey	  	1 bit
$Driver_Persist_Lid_Switch	1 bit
$Driver_Persist_PM	  	1 bit
$PersistHotkeyRestoreCloneMDS 	1 bit
$PersistHotkeyRestoreRefreshrate 1 bit
$PersistHotkeyRestorePipe	1 bit
$PersistHotkeyRestoreMode	1 bit
$PersistEDIDRestoreMode		1 bit
$PersistHotPlugRestoreMode	1 bit
$Driver_Persist_Docking		1 bit
      #IF	$Chipset == 8 		; $Chipset == CAL removed as per Driver team's requirement.
$PersistCRTHotplugRestoreMode   1 bit
SKIP                            5 bits
      #ELSE	 
SKIP		   		6 bits
      #ENDIF	
ALIGN
$PersistMaxConfig		1 byte
      #ENDIF	; $BIOS_Type == MOBILE


;==============================================================================
; Block 14 - Pointer tables
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size
SKIP			1 byte		; Number of tables

$Clock_Override_Table_Ptr	2 bytes
$Clock_Override_Table_Size	2 bytes
$Clock_Override_Table,		$Clock_Override_Table_Ptr, $Clock_Override_Table_Size, Offset 0 byte

      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$LVDS_Clock_Override_Tbl_Ptr	2 bytes
$LVDS_Clock_Override_Tbl_Size	2 bytes
$LVDS_Clock_Override_Tbl,	$LVDS_Clock_Override_Tbl_Ptr, $LVDS_Clock_Override_Tbl_Size, Offset 0 byte
      #ENDIF	; $Integrated_LVDS == TRUE


;==============================================================================
; Block 15 - Dot Clock Override Table.
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size
SKIP			2 bytes		; Table X and Y
SKIP			90 bytes	; Skip data

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
SKIP			47 bytes	; Skip LVDS data
      #ENDIF	; $BIOS_Type == MOBILE

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
;==============================================================================
; Block 16 - VBIOS/Driver Toggle list, capabilities tables
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size
SKIP			132 bytes	; Skip Toggle lists
ALIGN
      #ENDIF	; $BIOS_Type == MOBILE



;==============================================================================
; Block 17 - Test Feature
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$SV_Dis_Arbiter		1 bit		; Disable VGA fast arbiter
$SV_Setmode_No_DVO	1 bit		; Do Setmode without reprogramming DVO
$SV_Special_GMBus	1 bit		; Special GMBus support
$SV_Wait_Timeout_Hang	1 bit
SKIP			4 bits
ALIGN
SKIP			7 bytes		; Skip reserved space


;==============================================================================
; Block 18 - Driver Rotation Configuration
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size
$Rot_Enable		1 bit		; Rotation Enable bit
SKIP			7 bits		
$Rot_Flags		1 byte
SKIP			10 bytes	; Reserved


      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
;==============================================================================
; Block 19 - Removed Display Configurations
;------------------------------------------------------------------------------

SKIP			3  bytes		; Skip block ID and size
SKIP			2  bytes		; Table Row/Size Data
SKIP			30  bytes		; Skip Removed displays table
      #ENDIF	; $BIOS_Type == MOBILE


;==============================================================================
; Block 20 - OEM Customizable Modes
;------------------------------------------------------------------------------

SKIP			3  bytes		; Skip ID
SKIP			2  bytes		; Table Row/Size Data

$OEM_Mode_Flags1	1 byte
$OEM_Display_Flags1	1 byte
$OEM_Mode_X1		2 bytes
$OEM_Mode_Y1		2 bytes
$OEM_Mode_Color1	1 byte
$OEM_Mode_RRate1	1 byte
$OEM_Mode_DTD1		18 bytes

$OEM_Mode_Flags2	1 byte
$OEM_Display_Flags2	1 byte
$OEM_Mode_X2		2 bytes
$OEM_Mode_Y2		2 bytes
$OEM_Mode_Color2	1 byte
$OEM_Mode_RRate2	1 byte
$OEM_Mode_DTD2		18 bytes

$OEM_Mode_Flags3	1 byte
$OEM_Display_Flags3	1 byte
$OEM_Mode_X3		2 bytes
$OEM_Mode_Y3		2 bytes
$OEM_Mode_Color3	1 byte
$OEM_Mode_RRate3	1 byte
$OEM_Mode_DTD3		18 bytes

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
$OEM_Mode_Flags4	1 byte
$OEM_Display_Flags4	1 byte
$OEM_Mode_X4		2 bytes
$OEM_Mode_Y4		2 bytes
$OEM_Mode_Color4	1 byte
$OEM_Mode_RRate4	1 byte
$OEM_Mode_DTD4		18 bytes

$OEM_Mode_Flags5	1 byte
$OEM_Display_Flags5	1 byte
$OEM_Mode_X5		2 bytes
$OEM_Mode_Y5		2 bytes
$OEM_Mode_Color5	1 byte
$OEM_Mode_RRate5	1 byte
$OEM_Mode_DTD5		18 bytes

$OEM_Mode_Flags6	1 byte
$OEM_Display_Flags6	1 byte
$OEM_Mode_X6		2 bytes
$OEM_Mode_Y6		2 bytes
$OEM_Mode_Color6	1 byte
$OEM_Mode_RRate6	1 byte
$OEM_Mode_DTD6		18 bytes
      #ENDIF	; $BIOS_Type == MOBILE
      
;==============================================================================
; Block 22 - SDVO LVDS general parameters
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$LVDS_Init_Backlight 	1 byte
$LVDS_H40_Set_Panel_Type 1 byte
$LVDS_Panel_Type	1 byte
$LVDS_SSC_CLK_FREQ	1 byte
$LVDS_ALS_Low_Trip	2 bytes
$LVDS_ALS_High_Trip	2 bytes

SKIP			1 byte		; Skip Row Number
SKIP			1 byte		; Skip Row Size

$Scalar_Coef_0		1 byte
$Scalar_Coef_1		1 byte
$Scalar_Coef_2		1 byte
$Scalar_Coef_3		1 byte
$Scalar_Coef_4		1 byte
$Scalar_Coef_5		1 byte
$Scalar_Coef_6		1 byte
$Scalar_Coef_7		1 byte
		
		; LVDS_Misc_Bits_1.
		
$LVDS_Monitor_Hsync	1 bit
$LVDS_Monitor_Vsync	1 bit
$LVDS_Monitor_Pixel	1 bit
$LVDS_Panel_EDID	1 bit
$LVDS_Panel_Fitting	1 bit
$LVDS_Dither		1 bit
SKIP			2 bits

		; LVDS_Misc_Bits_2.
		
$LVDS_Panel_Color_Depth	2 bits
$LVDS_Panel_Connector	2 bits
$LVDS_Channel		2 bits
$LVDS_SSC_DualTwin_Disb	1 bit
$LVDS_SSC		1 bit

		; LVDS_Misc_Bits_3.

$LVDS_Panel_1_Channel_Type	1 bit
$LVDS_Panel_2_Channel_Type	1 bit
$LVDS_Panel_3_Channel_Type	1 bit
$LVDS_Panel_4_Channel_Type	1 bit
SKIP				4 bits

		; LVDS_Misc_Bits_4.

$LVDS_Panel_1_Color_Depth	2 bits
$LVDS_Panel_2_Color_Depth	2 bits
$LVDS_Panel_3_Color_Depth	2 bits
$LVDS_Panel_4_Color_Depth	2 bits
SKIP				1 byte

;==============================================================================
; Block 23 - SDVO Panel DTDs
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			18 bytes	; Panel#1 DTD
SKIP			18 bytes	; Panel#2 DTD
SKIP			18 bytes	; Panel#3 DTD
SKIP			18 bytes	; Panel#4 DTD

;==============================================================================
;  Block 24 - Tables of Panel PnP ID
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			10 bytes	; Panel#1 PnPID
SKIP			10 bytes	; Panel#2 PnPID
SKIP			10 bytes	; Panel#3 PnPID
SKIP			10 bytes	; Panel#4 PnPID

;==============================================================================
; Block #25 - SDVO LVDS Power Sequencing
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			10 bytes	; Panel#1 Power Sequencing
SKIP			10 bytes	; Panel#2 Power Sequencing
SKIP			10 bytes	; Panel#3 Power Sequencing
SKIP			10 bytes	; Panel#4 Power Sequencing

;==============================================================================
; Block 26 - TV features
;------------------------------------------------------------------------------
SKIP			3  bytes	; Skip ID and size
$Under_Over_Scan_Via_YPrPb 2 bits	; Underscan/overscan for HDTV via YPrPb
SKIP			10 bits
$Under_Over_Scan_Via_DVI 2 bits		; Underscan/overscan for HDTV via DVI
$Add_Overscan_Mode 	1 bit		; Add modes to avoid overscan issue
$D_Connector		1 bit		; D-Connector Support

      #IF	$eDP == 1	; $eDP == TRUE
;==============================================================================
; Block #27 - eDP Power Sequencing
;------------------------------------------------------------------------------
SKIP			3 bytes		; Skip block ID and size

SKIP			10 bytes		; Panel#1 Power Sequencing
SKIP			10 bytes		; Panel#2 Power Sequencing
SKIP			10 bytes		; Panel#3 Power Sequencing
SKIP			10 bytes		; Panel#4 Power Sequencing
SKIP			10 bytes		; Panel#5 Power Sequencing
SKIP			10 bytes		; Panel#6 Power Sequencing
SKIP			10 bytes		; Panel#7 Power Sequencing
SKIP			10 bytes		; Panel#8 Power Sequencing
SKIP			10 bytes		; Panel#9 Power Sequencing
SKIP			10 bytes		; Panel#10 Power Sequencing
SKIP			10 bytes		; Panel#11 Power Sequencing
SKIP			10 bytes		; Panel#12 Power Sequencing
SKIP			10 bytes		; Panel#13 Power Sequencing
SKIP			10 bytes		; Panel#14 Power Sequencing
SKIP			10 bytes		; Panel#15 Power Sequencing
SKIP			10 bytes		; Panel#16 Power Sequencing

$eDP_Panel_Color_Depth_01	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_02	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_03	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_04	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_05	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_06	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_07	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_08	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_09	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_10	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_11	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_12	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_13	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_14	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_15	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_16	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp

							
$eDP_Link_DataRate_01		4 bits	; Panel #1 Link Data Rate
$eDP_Link_LaneCount_01		4 bits	; Panel #1 Link Lane Count
$eDP_Link_PreEmp_01			4 bits	; Panel #1 Link Pre-emphasis
$eDP_Link_Vswing_01			4 bits	; Panel #1 Link Voltage Swing

$eDP_Link_DataRate_02		4 bits	; Panel #2 Link Data Rate
$eDP_Link_LaneCount_02		4 bits	; Panel #2 Link Lane Count
$eDP_Link_PreEmp_02			4 bits	; Panel #2 Link Pre-emphasis
$eDP_Link_Vswing_02			4 bits	; Panel #2 Link Voltage Swing

$eDP_Link_DataRate_03		4 bits	; Panel #3 Link Data Rate
$eDP_Link_LaneCount_03		4 bits	; Panel #3 Link Lane Count
$eDP_Link_PreEmp_03			4 bits	; Panel #3 Link Pre-emphasis
$eDP_Link_Vswing_03			4 bits	; Panel #3 Link Voltage Swing

$eDP_Link_DataRate_04		4 bits	; Panel #4 Link Data Rate	
$eDP_Link_LaneCount_04		4 bits 	; Panel #4 Link Lane Count	
$eDP_Link_PreEmp_04			4 bits	; Panel #4 Link Pre-emphasis
$eDP_Link_Vswing_04			4 bits	; Panel #4 Link Voltage Swing

$eDP_Link_DataRate_05		4 bits	; Panel #5 Link Data Rate
$eDP_Link_LaneCount_05		4 bits	; Panel #5 Link Lane Count
$eDP_Link_PreEmp_05			4 bits	; Panel #5 Link Pre-emphasis
$eDP_Link_Vswing_05			4 bits	; Panel #5 Link Voltage Swing

$eDP_Link_DataRate_06		4 bits	; Panel #6 Link Data Rate
$eDP_Link_LaneCount_06		4 bits	; Panel #6 Link Lane Count
$eDP_Link_PreEmp_06			4 bits	; Panel #6 Link Pre-emphasis
$eDP_Link_Vswing_06			4 bits	; Panel #6 Link Voltage Swing

$eDP_Link_DataRate_07		4 bits	; Panel #7 Link Data Rate
$eDP_Link_LaneCount_07		4 bits	; Panel #7 Link Lane Count
$eDP_Link_PreEmp_07			4 bits	; Panel #7 Link Pre-emphasis
$eDP_Link_Vswing_07			4 bits	; Panel #7 Link Voltage Swing

$eDP_Link_DataRate_08		4 bits	; Panel #8 Link Data Rate
$eDP_Link_LaneCount_08		4 bits	; Panel #8 Link Lane Count
$eDP_Link_PreEmp_08			4 bits	; Panel #8 Link Pre-emphasis
$eDP_Link_Vswing_08			4 bits	; Panel #8 Link Voltage Swing

$eDP_Link_DataRate_09		4 bits	; Panel #9 Link Data Rate
$eDP_Link_LaneCount_09		4 bits	; Panel #9 Link Lane Count
$eDP_Link_PreEmp_09			4 bits	; Panel #9 Link Pre-emphasis
$eDP_Link_Vswing_09			4 bits	; Panel #9 Link Voltage Swing

$eDP_Link_DataRate_10		4 bits	; Panel #10 Link Data Rate
$eDP_Link_LaneCount_10		4 bits	; Panel #10 Link Lane Count
$eDP_Link_PreEmp_10			4 bits	; Panel #10 Link Pre-emphasis
$eDP_Link_Vswing_10			4 bits	; Panel #10 Link Voltage Swing

$eDP_Link_DataRate_11		4 bits	; Panel #11 Link Data Rate
$eDP_Link_LaneCount_11		4 bits	; Panel #11 Link Lane Count
$eDP_Link_PreEmp_11			4 bits	; Panel #11 Link Pre-emphasis
$eDP_Link_Vswing_11			4 bits	; Panel #11 Link Voltage Swing

$eDP_Link_DataRate_12		4 bits	; Panel #12 Link Data Rate
$eDP_Link_LaneCount_12		4 bits	; Panel #12 Link Lane Count
$eDP_Link_PreEmp_12			4 bits	; Panel #12 Link Pre-emphasis
$eDP_Link_Vswing_12			4 bits	; Panel #12 Link Voltage Swing

$eDP_Link_DataRate_13		4 bits	; Panel #13 Link Data Rate
$eDP_Link_LaneCount_13		4 bits	; Panel #13 Link Lane Count
$eDP_Link_PreEmp_13			4 bits	; Panel #13 Link Pre-emphasis
$eDP_Link_Vswing_13			4 bits	; Panel #13 Link Voltage Swing

$eDP_Link_DataRate_14		4 bits	; Panel #14 Link Data Rate
$eDP_Link_LaneCount_14		4 bits	; Panel #14 Link Lane Count
$eDP_Link_PreEmp_14			4 bits	; Panel #14 Link Pre-emphasis
$eDP_Link_Vswing_14			4 bits	; Panel #14 Link Voltage Swing

$eDP_Link_DataRate_15		4 bits	; Panel #15 Link Data Rate
$eDP_Link_LaneCount_15		4 bits	; Panel #15 Link Lane Count
$eDP_Link_PreEmp_15			4 bits	; Panel #15 Link Pre-emphasis
$eDP_Link_Vswing_15			4 bits	; Panel #15 Link Voltage Swing

$eDP_Link_DataRate_16		4 bits	; Panel #16 Link Data Rate
$eDP_Link_LaneCount_16		4 bits	; Panel #16 Link Lane Count
$eDP_Link_PreEmp_16			4 bits	; Panel #16 Link Pre-emphasis
$eDP_Link_Vswing_16			4 bits	; Panel #16 Link Voltage Swing


      #ENDIF	; $eDP == 1	; $eDP == TRUE


      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
;==============================================================================
; Block 40 - Start of LVDS BMP Structure Definition
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$bmp_Panel_type		1 byte		; Flat panel type
SKIP			1 byte		; Obsoleted
SKIP			6 bits
$bmp_Panel_EDID		1 bit		; LVDS panel EDID enable/disable bit
SKIP			1 bit
SKIP			1 byte

		; INT_LVDS_Panel_Channel_Bits
	
$Int_LVDS_Panel_1_Channel_Type	2 bits	; Bits [2:3] = Panel #1
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_2_Channel_Type	2 bits	; Bits [2:3] = Panel #2
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_3_Channel_Type	2 bits	; Bits [2:3] = Panel #3
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_4_Channel_Type	2 bits	; Bits [2:3] = Panel #4
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_5_Channel_Type	2 bits	; Bits [2:3] = Panel #5
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_6_Channel_Type	2 bits	; Bits [2:3] = Panel #6
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_7_Channel_Type	2 bits	; Bits [2:3] = Panel #7
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_8_Channel_Type	2 bits	; Bits [2:3] = Panel #8
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_9_Channel_Type	2 bits	; Bits [2:3] = Panel #9
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_10_Channel_Type	2 bits	; Bits [2:3] = Panel #10
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_11_Channel_Type	2 bits	; Bits [2:3] = Panel #11
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_12_Channel_Type	2 bits	; Bits [2:3] = Panel #12
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_13_Channel_Type	2 bits	; Bits [2:3] = Panel #13
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_14_Channel_Type	2 bits	; Bits [2:3] = Panel #14
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_15_Channel_Type	2 bits	; Bits [2:3] = Panel #15
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_16_Channel_Type	2 bits	; Bits [2:3] = Panel #16
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
      
      #IF	$BIOS_Type == 1 && ($Chipset >= 8 || $Chipset == 2 ); Mobile && ( CAL or CRL )
					; LVDS Spread Spectrum Clock
					; Enabel/Disable SSC
$Enable_SSC01		1 bit		; Panel #01, 0=No, 1=Yes
$Enable_SSC02		1 bit		; Panel #02, 0=No, 1=Yes
$Enable_SSC03		1 bit		; Panel #03, 0=No, 1=Yes
$Enable_SSC04		1 bit		; Panel #04, 0=No, 1=Yes
$Enable_SSC05		1 bit		; Panel #05, 0=No, 1=Yes
$Enable_SSC06		1 bit		; Panel #06, 0=No, 1=Yes
$Enable_SSC07		1 bit		; Panel #07, 0=No, 1=Yes
$Enable_SSC08		1 bit		; Panel #08, 0=No, 1=Yes
$Enable_SSC09		1 bit		; Panel #09, 0=No, 1=Yes
$Enable_SSC10		1 bit		; Panel #10, 0=No, 1=Yes
$Enable_SSC11		1 bit		; Panel #11, 0=No, 1=Yes
$Enable_SSC12		1 bit		; Panel #12, 0=No, 1=Yes
$Enable_SSC13		1 bit		; Panel #13, 0=No, 1=Yes
$Enable_SSC14		1 bit		; Panel #14, 0=No, 1=Yes
$Enable_SSC15		1 bit		; Panel #15, 0=No, 1=Yes
$Enable_SSC16		1 bit		; Panel #16, 0=No, 1=Yes

					; LVDS Spread Spectrum Clock Frequency
					; SSC Frequency
$SSC_Freq01		1 bit		; Panel #01, 0=48MHz, 1=66MHz
$SSC_Freq02		1 bit		; Panel #02, 0=48MHz, 1=66MHz
$SSC_Freq03		1 bit		; Panel #03, 0=48MHz, 1=66MHz
$SSC_Freq04		1 bit		; Panel #04, 0=48MHz, 1=66MHz
$SSC_Freq05		1 bit		; Panel #05, 0=48MHz, 1=66MHz
$SSC_Freq06		1 bit		; Panel #06, 0=48MHz, 1=66MHz
$SSC_Freq07		1 bit		; Panel #07, 0=48MHz, 1=66MHz
$SSC_Freq08		1 bit		; Panel #08, 0=48MHz, 1=66MHz
$SSC_Freq09		1 bit		; Panel #09, 0=48MHz, 1=66MHz
$SSC_Freq10		1 bit		; Panel #10, 0=48MHz, 1=66MHz
$SSC_Freq11		1 bit		; Panel #11, 0=48MHz, 1=66MHz
$SSC_Freq12		1 bit		; Panel #12, 0=48MHz, 1=66MHz
$SSC_Freq13		1 bit		; Panel #13, 0=48MHz, 1=66MHz
$SSC_Freq14		1 bit		; Panel #14, 0=48MHz, 1=66MHz
$SSC_Freq15		1 bit		; Panel #15, 0=48MHz, 1=66MHz
$SSC_Freq16		1 bit		; Panel #16, 0=48MHz, 1=66MHz

					; Disable SSC in Dual Display Twin
$Disable_SSC_DDT01	1 bit		; panel #01, 0=Disable, 1=Enable
$Disable_SSC_DDT02	1 bit		; panel #02, 0=Disable, 1=Enable
$Disable_SSC_DDT03	1 bit		; panel #03, 0=Disable, 1=Enable
$Disable_SSC_DDT04	1 bit		; panel #04, 0=Disable, 1=Enable
$Disable_SSC_DDT05	1 bit		; panel #05, 0=Disable, 1=Enable
$Disable_SSC_DDT06	1 bit		; panel #06, 0=Disable, 1=Enable
$Disable_SSC_DDT07	1 bit		; panel #07, 0=Disable, 1=Enable
$Disable_SSC_DDT08	1 bit		; panel #08, 0=Disable, 1=Enable
$Disable_SSC_DDT09	1 bit		; panel #09, 0=Disable, 1=Enable
$Disable_SSC_DDT10	1 bit		; panel #10, 0=Disable, 1=Enable
$Disable_SSC_DDT11	1 bit		; panel #11, 0=Disable, 1=Enable
$Disable_SSC_DDT12	1 bit		; panel #12, 0=Disable, 1=Enable
$Disable_SSC_DDT13	1 bit		; panel #13, 0=Disable, 1=Enable
$Disable_SSC_DDT14	1 bit		; panel #14, 0=Disable, 1=Enable
$Disable_SSC_DDT15	1 bit		; panel #15, 0=Disable, 1=Enable
$Disable_SSC_DDT16	1 bit		; panel #16, 0=Disable, 1=Enable
      #ENDIF	; $BIOS_Type == 1 && $Chipset >= 8
      
      #IF	$BIOS_Type == 1 && $Chipset >= 10	; Mobile && ( CRL OR CTG )
$INT_Panel_Color_Depth01	1 bit		; Panel #01, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth02	1 bit		; Panel #02, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth03	1 bit		; Panel #03, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth04	1 bit		; Panel #04, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth05	1 bit		; Panel #05, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth06	1 bit		; Panel #06, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth07	1 bit		; Panel #07, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth08	1 bit		; Panel #08, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth09	1 bit		; Panel #09, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth10	1 bit		; Panel #10, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth11	1 bit		; Panel #11, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth12	1 bit		; Panel #12, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth13	1 bit		; Panel #13, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth14	1 bit		; Panel #14, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth15	1 bit		; Panel #15, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth16	1 bit		; Panel #16, 0 = 18bpps, 1 = 24bpps
      #ENDIF	; $BIOS_Type == 1 && $Chipset == 10

      #IF	$Chipset == 13; CTG
$DPS_Panel_Type_01		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_02		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_03		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_04		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_05		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_06		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_07		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_08		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_09		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_10		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_11		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_12		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_13		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_14		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_15		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
$DPS_Panel_Type_16		2 bits		; 00 = Static DRRS, 01 = D2PO, 10 = Seamless
     #ENDIF    ; $Chipset == 13

      #ENDIF	; $Integrated_LVDS == TRUE
	

      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
;==============================================================================
; Block 41 - Flat Panel Data Tables Pointers
;------------------------------------------------------------------------------

SKIP			3 bytes		; SKIP block ID and size
SKIP			1 byte		; Skip entries number byte

$LVDS_Tbl_Ptr_01	2 bytes
$LVDS_Tbl_Size_01	1 byte
$LVDS_Tbl_01,		$LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes
$DVO_Tbl_Ptr_01		2 bytes
$DVO_Tbl_Size_01	1 byte
$DVO_Tbl_01,		$DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte
$LVDS_PnP_ID_Ptr_01	2 bytes
$LVDS_PnP_ID_Size_01	1 byte
$LVDS_PnP_ID_01,	$LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte

$LVDS_Tbl_Ptr_02	2 bytes
$LVDS_Tbl_Size_02	1 byte
$LVDS_Tbl_02,		$LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes
$DVO_Tbl_Ptr_02		2 bytes
$DVO_Tbl_Size_02	1 byte
$DVO_Tbl_02,		$DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte
$LVDS_PnP_ID_Ptr_02	2 bytes
$LVDS_PnP_ID_Size_02	1 byte
$LVDS_PnP_ID_02,	$LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte

$LVDS_Tbl_Ptr_03	2 bytes
$LVDS_Tbl_Size_03	1 byte
$LVDS_Tbl_03,		$LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes
$DVO_Tbl_Ptr_03		2 bytes
$DVO_Tbl_Size_03	1 byte
$DVO_Tbl_03,		$DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte
$LVDS_PnP_ID_Ptr_03	2 bytes
$LVDS_PnP_ID_Size_03	1 byte
$LVDS_PnP_ID_03,	$LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte

$LVDS_Tbl_Ptr_04	2 bytes
$LVDS_Tbl_Size_04	1 byte
$LVDS_Tbl_04,		$LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes
$DVO_Tbl_Ptr_04		2 bytes
$DVO_Tbl_Size_04	1 byte
$DVO_Tbl_04,		$DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte
$LVDS_PnP_ID_Ptr_04	2 bytes
$LVDS_PnP_ID_Size_04	1 byte
$LVDS_PnP_ID_04,	$LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte

$LVDS_Tbl_Ptr_05	2 bytes
$LVDS_Tbl_Size_05	1 byte
$LVDS_Tbl_05,		$LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes
$DVO_Tbl_Ptr_05		2 bytes
$DVO_Tbl_Size_05	1 byte
$DVO_Tbl_05,		$DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte
$LVDS_PnP_ID_Ptr_05	2 bytes
$LVDS_PnP_ID_Size_05	1 byte
$LVDS_PnP_ID_05,	$LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte

$LVDS_Tbl_Ptr_06	2 bytes
$LVDS_Tbl_Size_06	1 byte
$LVDS_Tbl_06,		$LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes
$DVO_Tbl_Ptr_06		2 bytes
$DVO_Tbl_Size_06	1 byte
$DVO_Tbl_06,		$DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte
$LVDS_PnP_ID_Ptr_06	2 bytes
$LVDS_PnP_ID_Size_06	1 byte
$LVDS_PnP_ID_06,	$LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte

$LVDS_Tbl_Ptr_07	2 bytes
$LVDS_Tbl_Size_07	1 byte
$LVDS_Tbl_07,		$LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes
$DVO_Tbl_Ptr_07		2 bytes
$DVO_Tbl_Size_07	1 byte
$DVO_Tbl_07,		$DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte
$LVDS_PnP_ID_Ptr_07	2 bytes
$LVDS_PnP_ID_Size_07	1 byte
$LVDS_PnP_ID_07,	$LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte

$LVDS_Tbl_Ptr_08	2 bytes
$LVDS_Tbl_Size_08	1 byte
$LVDS_Tbl_08,		$LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes
$DVO_Tbl_Ptr_08		2 bytes
$DVO_Tbl_Size_08	1 byte
$DVO_Tbl_08,		$DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte
$LVDS_PnP_ID_Ptr_08	2 bytes
$LVDS_PnP_ID_Size_08	1 byte
$LVDS_PnP_ID_08,	$LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte

$LVDS_Tbl_Ptr_09	2 bytes
$LVDS_Tbl_Size_09	1 byte
$LVDS_Tbl_09,		$LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes
$DVO_Tbl_Ptr_09		2 bytes
$DVO_Tbl_Size_09	1 byte
$DVO_Tbl_09,		$DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte
$LVDS_PnP_ID_Ptr_09	2 bytes
$LVDS_PnP_ID_Size_09	1 byte
$LVDS_PnP_ID_09,	$LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte

$LVDS_Tbl_Ptr_10	2 bytes
$LVDS_Tbl_Size_10	1 byte
$LVDS_Tbl_10,		$LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes
$DVO_Tbl_Ptr_10		2 bytes
$DVO_Tbl_Size_10	1 byte
$DVO_Tbl_10,		$DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte
$LVDS_PnP_ID_Ptr_10	2 bytes
$LVDS_PnP_ID_Size_10	1 byte
$LVDS_PnP_ID_10,	$LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte

$LVDS_Tbl_Ptr_11	2 bytes
$LVDS_Tbl_Size_11	1 byte
$LVDS_Tbl_11,		$LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes
$DVO_Tbl_Ptr_11		2 bytes
$DVO_Tbl_Size_11	1 byte
$DVO_Tbl_11,		$DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte
$LVDS_PnP_ID_Ptr_11	2 bytes
$LVDS_PnP_ID_Size_11	1 byte
$LVDS_PnP_ID_11,	$LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte

$LVDS_Tbl_Ptr_12	2 bytes
$LVDS_Tbl_Size_12	1 byte
$LVDS_Tbl_12,		$LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes
$DVO_Tbl_Ptr_12		2 bytes
$DVO_Tbl_Size_12	1 byte
$DVO_Tbl_12,		$DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte
$LVDS_PnP_ID_Ptr_12	2 bytes
$LVDS_PnP_ID_Size_12	1 byte
$LVDS_PnP_ID_12,	$LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte

$LVDS_Tbl_Ptr_13	2 bytes
$LVDS_Tbl_Size_13	1 byte
$LVDS_Tbl_13,		$LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes
$DVO_Tbl_Ptr_13		2 bytes
$DVO_Tbl_Size_13	1 byte
$DVO_Tbl_13,		$DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte
$LVDS_PnP_ID_Ptr_13	2 bytes
$LVDS_PnP_ID_Size_13	1 byte
$LVDS_PnP_ID_13,	$LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte

$LVDS_Tbl_Ptr_14	2 bytes
$LVDS_Tbl_Size_14	1 byte
$LVDS_Tbl_14,		$LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes
$DVO_Tbl_Ptr_14		2 bytes
$DVO_Tbl_Size_14	1 byte
$DVO_Tbl_14,		$DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte
$LVDS_PnP_ID_Ptr_14	2 bytes
$LVDS_PnP_ID_Size_14	1 byte
$LVDS_PnP_ID_14,	$LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte

$LVDS_Tbl_Ptr_15	2 bytes
$LVDS_Tbl_Size_15	1 byte
$LVDS_Tbl_15,		$LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes
$DVO_Tbl_Ptr_15		2 bytes
$DVO_Tbl_Size_15	1 byte
$DVO_Tbl_15,		$DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte
$LVDS_PnP_ID_Ptr_15	2 bytes
$LVDS_PnP_ID_Size_15	1 byte
$LVDS_PnP_ID_15,	$LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte

$LVDS_Tbl_Ptr_16	2 bytes
$LVDS_Tbl_Size_16	1 byte
$LVDS_Tbl_16,		$LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes
$DVO_Tbl_Ptr_16		2 bytes
$DVO_Tbl_Size_16	1 byte
$DVO_Tbl_16,		$DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte
$LVDS_PnP_ID_Ptr_16	2 bytes
$LVDS_PnP_ID_Size_16	1 byte
$LVDS_PnP_ID_16,	$LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte
      #ENDIF	; $Integrated_LVDS == TRUE


      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
;==============================================================================
; Block 42 - Flat Panel Data Tables
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

			; Flat Panel #1

$Panel_Width_01		2 bytes		; Panel Width
$Panel_Height_01	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither01				1 bit	; Panel #01, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	; address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_01		13 bits	; Power on Backlight Enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_01				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	; address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_01	13 bits	;Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_01				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_01				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #2

$Panel_Width_02		2 bytes		; Panel Width
$Panel_Height_02	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither02				1 bit	; Panel #02, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_02		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_02				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_02	13 bits	; Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_02				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_02				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #3

$Panel_Width_03		2 bytes		; Panel Width
$Panel_Height_03	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither03				1 bit	; Panel #03, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_03		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_03				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_03	13 bits	; Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_03				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;aaddress-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_03				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #4

$Panel_Width_04		2 bytes		; Panel Width
$Panel_Height_04	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither04				1 bit	; Panel #04, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_04		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_04				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_04	13 bits	; Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_04				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_04				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #5

$Panel_Width_05		2 bytes		; Panel Width
$Panel_Height_05	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither05				1 bit	; Panel #05, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_05		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_05				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_05	13 bits	; Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_05				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_05				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #6

$Panel_Width_06		2 bytes		; Panel Width
$Panel_Height_06	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither06				1 bit	; Panel #06, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_06		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_06				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_06	13 bits	; Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_06				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_06				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control	

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #7

$Panel_Width_07		2 bytes		; Panel Width
$Panel_Height_07	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither07				1 bit	; Panel #07, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_07		13 bits	; Power on Backlight enable delay delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_07				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_07	13 bits	; Backlight off delay power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_07				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_07				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #8

$Panel_Width_08		2 bytes		; Panel Width
$Panel_Height_08	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither08				1 bit	; Panel #08, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_08		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_08				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_08	13 bits	; Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_08				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_08				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #9

$Panel_Width_09		2 bytes		; Panel Width
$Panel_Height_09	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither09				1 bit	; Panel #09, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_09		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_09				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_09	13 bits	;Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_09				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_09				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #10

$Panel_Width_10		2 bytes		; Panel Width
$Panel_Height_10	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither10				1 bit	; Panel #10, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_10		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_10				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_10	13 bits	;Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_10				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_10				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #11

$Panel_Width_11		2 bytes		; Panel Width
$Panel_Height_11	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither11				1 bit	; Panel #11, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_11		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_11				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_11	13 bits	; Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_11				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_11				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #12

$Panel_Width_12		2 bytes		; Panel Width
$Panel_Height_12	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither12				1 bit	; Panel #12, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_12		13 bits	; Powen on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_12				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_12	13 bits	; Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_12				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_12				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #13

$Panel_Width_13		2 bytes		; Panel Width
$Panel_Height_13	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither13				1 bit	; Panel #13, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_13		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_13				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_13	13 bits	;Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_13				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_13				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #14

$Panel_Width_14		2 bytes		; Panel Width
$Panel_Height_14	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither14				1 bit	; Panel #14, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_14		13 bits	; Power on baklight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_14				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_14	13 bits	;Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_14				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_14				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #15

$Panel_Width_15		2 bytes		; Panel Width
$Panel_Height_15	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither15				1 bit	; Panel #15, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_15		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_15				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_15	13 bits	; Backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_15				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_15				5 bits	; Power Cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID

			; Flat Panel #16

$Panel_Width_16		2 bytes		; Panel Width
$Panel_Height_16	2 bytes		; Panel Height

SKIP						4 bytes	;address-0x61180 - Port control
SKIP						3 bytes	; bits[23:0]
SKIP						1 bit	; bit[24]
$Enable_Dither16				1 bit	; Panel #16, 0=No, 1=Yes
SKIP						6 bits	; bits[31:26]
ALIGN

SKIP						4 bytes	;address-0x61208 - Panel power on sequencing
$Power_On_Backlight_Enable_Delay_16		13 bits	; Power on backlight enable delay
SKIP						3 bits	; bits[15:13]
$PowerUpDelay_16				13 bits	; Power up delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x6120C-Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_16	13 bits	; backlight off power down delay
SKIP						3 bits	; bits[15:13]
$PowerDownDelay_16				13 bits	; Power down delay
SKIP						3 bits	; bits[31:29]
ALIGN

SKIP						4 bytes	;address-0x61210h-Panel power cycle delay and reference divider
$PowerCycleDelay_16				5 bits	; Power cycle delay
SKIP						3 bits	; bits[5:7]
SKIP						3 bytes

SKIP						8 bytes	; Register offset 0x61230h-Panel fitting control

SKIP						2 bytes ; 2 bytes at the end

SKIP			18 bytes	; DTD
SKIP			10 bytes	; PnP ID
      #ENDIF	; $Integrated_LVDS == TRUE


      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
;==============================================================================
; Block 43 - BLC (Backlight Control) Support
;------------------------------------------------------------------------------

SKIP			3  bytes	; Skip block ID and size
SKIP			1  byte		; Skip row size

			; Flat Panel #1

$BLC_Inv_Type_1		2  bits		; BLC inverter type
$BLC_Inv_Polarity_1	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_1	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_1	2  bits		; BLC inverter GMBus speed

$PWM_Frequency_1	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_1	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 || $Chipset == 2)	; LVDS and $CS >= Alviso
$BLC_I2C_Addr_1		1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_1	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #2

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_2		2  bits		; BLC inverter type
$BLC_Inv_Polarity_2	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_2	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_2	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_2	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_2	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2)	; LVDS and $CS >= Alviso
$BLC_I2C_Addr_2		1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_2	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #3

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_3		2  bits		; BLC inverter type
$BLC_Inv_Polarity_3	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_3	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_3	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_3	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_3	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_3		1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_3	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #4

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_4		2  bits		; BLC inverter type
$BLC_Inv_Polarity_4	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_4	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_4	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_4	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_4	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_4		1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_4	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #5

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_5		2  bits		; BLC inverter type
$BLC_Inv_Polarity_5	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_5	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_5	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_5	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_5	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_5		1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_5	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #6

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_6		2  bits		; BLC inverter type
$BLC_Inv_Polarity_6	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_6	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_6	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_6	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_6	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_6		1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_6	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #7

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_7		2  bits		; BLC inverter type
$BLC_Inv_Polarity_7	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_7	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_7	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_7	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_7	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_7		1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_7	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #8

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_8		2  bits		; BLC inverter type
$BLC_Inv_Polarity_8	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_8	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_8	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_8	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_8	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_8		1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_8	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #9

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_9		2  bits		; BLC inverter type
$BLC_Inv_Polarity_9	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_9	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_9	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_9	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_9	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_9		1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_9	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #10

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_10    	2  bits		; BLC inverter type
$BLC_Inv_Polarity_10	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_10	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_10	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_10	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_10	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_10	1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_10	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #11

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_11	2  bits		; BLC inverter type
$BLC_Inv_Polarity_11	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_11	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_11	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_11	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_11	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_11	1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_11	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #12

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_12	2  bits		; BLC inverter type
$BLC_Inv_Polarity_12	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_12	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_12	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_12	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_12	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_12	1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_12	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #13

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_13	2  bits		; BLC inverter type
$BLC_Inv_Polarity_13	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_13	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_13	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_13	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_13	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_13	1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_13	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #14

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_14	2  bits		; BLC inverter type
$BLC_Inv_Polarity_14	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_14	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_14	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_14	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_14	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_14	1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_14	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #15

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_15    	2  bits		; BLC inverter type
$BLC_Inv_Polarity_15	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_15	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_15	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_15	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_15	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_15	1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_15	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso

			; Flat Panel #16

     #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
$BLC_Inv_Type_16	2  bits		; BLC inverter type
$BLC_Inv_Polarity_16	1  bit		; BLC inverter polarity
$BLC_GPIO_Pins_16	3  bits		; BLC inverter GPIO Pins
$BLC_GMBus_Speed_16	2  bits		; BLC inverter GMBus speed
$PWM_Frequency_16	2  bytes	; PWM inverter frequency
$BLC_Min_Brightness_16	1  byte		; Minimum Brightness, 0 - 255
     #ENDIF	; $Integrated_LVDS == TRUE
     #IF	$Integrated_LVDS == 1 && ($Chipset >= 5 ||  $Chipset == 2); LVDS and $CS >= Alviso
$BLC_I2C_Addr_16	1  byte		; I2C inverter Slave address
$BLC_Brightness_Cmd_16	1  byte		; I2C inverter command code
     #ENDIF	; LVDS and $CS >= Alviso


      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
;==============================================================================
; Block 44 - BIA (Backlight Image Adaption) Support
;------------------------------------------------------------------------------

SKIP			3  bytes	; Skip block ID and size

$BIA_Enable		1  bit		; DPST support enable bit
$BIA_Aggress_Level	3  bits		; Power Conservation Preference level
SKIP			3  bits		; Reserved
$ALS_Enable		1  bit		; ALS enable bit
$ALS_Response_Data	20  bytes	; ALS Response Data
      #ENDIF	; $Integrated_LVDS == TRUE

EndStruct


;==============================================================================
; List Definitions
;------------------------------------------------------------------------------

      #IF	$Integrated_LVDS == 1 ; $Integrated_LVDS == TRUE
List &Pwr_Pref_List
	Selection	0x01,	"1 - Maximum Quality with No DPST"
	Selection	0x02,	"2"
	Selection	0x03,	"3"
	Selection	0x04,	"4"
	Selection	0x05,	"5"
	Selection	0x06,	"6 - Maximum Battery"
EndList
      #ENDIF	; $Integrated_LVDS == TRUE

List &Clock_List
	Selection	4,	"04 Mhz"
	Selection	5,	"05 Mhz"
	Selection	6,	"06 Mhz"
	Selection	7,	"07 Mhz"
	Selection	8,	"08 Mhz"
	Selection	9,	"09 Mhz"
	Selection	10,	"10 Mhz"
	Selection	11,	"11 Mhz"
	Selection	12,	"12 Mhz"
	Selection	13,	"13 Mhz"
	Selection	14,	"14 Mhz"
	Selection	15,	"15 Mhz"
	Selection	16,	"16 Mhz"
	Selection	17,	"17 Mhz"
	Selection	18,	"18 Mhz"
	Selection	19,	"19 Mhz"
	Selection	20,	"20 Mhz"
	Selection	21,	"21 Mhz"
	Selection	22,	"22 Mhz"
	Selection	23,	"23 Mhz"
	Selection	24,	"24 Mhz"
	Selection	25,	"25 Mhz"
	Selection	26,	"26 Mhz"
	Selection	27,	"27 Mhz"
	Selection	28,	"28 Mhz"
	Selection	29,	"29 Mhz"
	Selection	30,	"30 Mhz"
	Selection	31,	"31 Mhz"
	Selection	32,	"32 Mhz"
	Selection	33,	"33 Mhz"
	Selection	34,	"34 Mhz"
	Selection	35,	"35 Mhz"
	Selection	36,	"36 Mhz"
	Selection	37,	"37 Mhz"
	Selection	38,	"38 Mhz"
	Selection	39,	"39 Mhz"
	Selection	40,	"40 Mhz"
	Selection	41,	"41 Mhz"
	Selection	42,	"42 Mhz"
	Selection	43,	"43 Mhz"
	Selection	44,	"44 Mhz"
	Selection	45,	"45 Mhz"
	Selection	46,	"46 Mhz"
	Selection	47,	"47 Mhz"
	Selection	48,	"48 Mhz"
	Selection	49,	"49 Mhz"
	Selection	50,	"50 Mhz"
	Selection	51,	"51 Mhz"
	Selection	52,	"52 Mhz"
	Selection	53,	"53 Mhz"
	Selection	54,	"54 Mhz"
	Selection	55,	"55 Mhz"
	Selection	56,	"56 Mhz"
	Selection	57,	"57 Mhz"
	Selection	58,	"58 Mhz"
	Selection	59,	"59 Mhz"
	Selection	60,	"60 Mhz"
	Selection	61,	"61 Mhz"
	Selection	62,	"62 Mhz"
	Selection	63,	"63 Mhz"
	Selection	64,	"64 Mhz"
	Selection	65,	"65 Mhz"
	Selection	66,	"66 Mhz"
	Selection	67,	"67 Mhz"
	Selection	68,	"68 Mhz"
	Selection	69,	"69 Mhz"
	Selection	70,	"70 Mhz"
	Selection	71,	"71 Mhz"
	Selection	72,	"72 Mhz"
	Selection	73,	"73 Mhz"
	Selection	74,	"74 Mhz"
	Selection	75,	"75 Mhz"
	Selection	76,	"76 Mhz"
	Selection	77,	"77 Mhz"
	Selection	78,	"78 Mhz"
	Selection	79,	"79 Mhz"
	Selection	80,	"80 Mhz"
	Selection	81,	"81 Mhz"
	Selection	82,	"82 Mhz"
	Selection	83,	"83 Mhz"
	Selection	84,	"84 Mhz"
	Selection	85,	"85 Mhz"
	Selection	86,	"86 Mhz"
	Selection	87,	"87 Mhz"
	Selection	88,	"88 Mhz"
	Selection	89,	"89 Mhz"
	Selection	90,	"90 Mhz"
	Selection	91,	"91 Mhz"
	Selection	92,	"92 Mhz"
	Selection	93,	"93 Mhz"
	Selection	94,	"94 Mhz"
	Selection	95,	"95 Mhz"
	Selection	96,	"96 Mhz"
	Selection	97,	"97 Mhz"
	Selection	98,	"98 Mhz"
	Selection	99,	"99 Mhz"
	Selection	100,	"100 Mhz"
	Selection	101,	"101 Mhz"
	Selection	102,	"102 Mhz"
	Selection	103,	"103 Mhz"
	Selection	104,	"104 Mhz"
	Selection	105,	"105 Mhz"
	Selection	106,	"106 Mhz"
	Selection	107,	"107 Mhz"
	Selection	108,	"108 Mhz"
	Selection	109,	"109 Mhz"
	Selection	110,	"110 Mhz"
	Selection	111,	"111 Mhz"
	Selection	112,	"112 Mhz"
	Selection	113,	"113 Mhz"
	Selection	114,	"114 Mhz"
	Selection	115,	"115 Mhz"
	Selection	116,	"116 Mhz"
	Selection	117,	"117 Mhz"
	Selection	118,	"118 Mhz"
	Selection	119,	"119 Mhz"
	Selection	120,	"120 Mhz"
	Selection	121,	"121 Mhz"
	Selection	122,	"122 Mhz"
	Selection	123,	"123 Mhz"
	Selection	124,	"124 Mhz"
	Selection	125,	"125 Mhz"
	Selection	126,	"126 Mhz"
	Selection	127,	"127 Mhz"
	Selection	128,	"128 Mhz"
	Selection	129,	"129 Mhz"
	Selection	130,	"130 Mhz"
	Selection	131,	"131 Mhz"
	Selection	132,	"132 Mhz"
	Selection	133,	"133 Mhz"
	Selection	134,	"134 Mhz"
	Selection	135,	"135 Mhz"
EndList

List &Cls_After_Signon_List
	Selection	0x00,	"No CLS"
	Selection	0x01,	"0.5 Second Delay + CLS"
	Selection	0x02,	"1.0 Second Delay + CLS"
	Selection	0x03,	"1.5 Second Delay + CLS"
	Selection	0x04,	"2.0 Second Delay + CLS"
	Selection	0x05,	"2.5 Second Delay + CLS"
	Selection	0x06,	"3.0 Second Delay + CLS"
	Selection	0x07,	"3.5 Second Delay + CLS"
EndList

List &Device_Type_List
	Selection	0x0000,	"No Device"
	Selection	0x6001, "Analog CRT - VESA DPMS"
;	Selection	0x4001, "Analog CRT - VESA DPMS & Hot Plug"

;	Selection	0x0209, "Analog TV - Composite Video Out"
;	Selection	0x0289, "Analog TV - Macrovison"
;	Selection	0x020C, "Analog TV - RF Tuner and Composite Video Out"
	Selection	0x0609, "Analog TV - Composite and S-Video Out"
;	Selection	0x0209, "Analog TV - SCART Video Connector"
;	Selection	0x6009, "Analog TV - Codec supported HotPlug and Power Management"

;	Selection	0x6012, "EFP - Hotplug and Power Management"
				; $Chipset == (BWG || CRL || BLB || CTG || ELK)
      #IF	($Chipset == 9) || ($Chipset == 10) || ($Chipset == 12) || ($Chipset == 13) || ($Chipset == 14)
	Selection	0x6852, "EFP - DVI 1.0 Codec with HotPlug and Power Management"
	Selection	0x6853, "EFP - DVI-I (Analog & Digital Connector)"
      #ELSE
	Selection	0x6052, "EFP - DVI 1.0 Codec with HotPlug and Power Management"
	Selection	0x6053, "EFP - DVI-I (Analog & Digital Connector)"
      #ENDIF	; 
;	Selection	0x6152, "EFP - Dual Channel DVI-D"
;	Selection	0x60D2, "EFP - DVI-D & HDCP"
;	Selection	0x6062, "OpenLDI with HotPlug and Power Management"
;	Selection	0x6162, "OpenLDI with DualPixel Support"

;	Selection	0x5012, "LFP - PanelLink"
;	Selection	0x5042, "LFP - CMOS with Power Management"
	Selection	0x5062, "LFP - LVDS with Power Management"
;	Selection	0x5162, "LFP - Dual-Channel LVDS"
;	Selection	0x51E2, "LFP - Dual-Channel LVDS with HDCP"

;	Selection	0xF0D2, "Integrated HDMI"
				; $Chipset == (BWG || CRL || BLB || CTG || ELK)
      #IF	($Chipset == 9) || ($Chipset == 10) || ($Chipset == 12) || ($Chipset == 13) || ($Chipset == 14)
	Selection	0x60D2, "HDMI - Hotplug and Power Management"
      #ENDIF	; ($Chipset == 8) ||($Chipset == 10)
EndList

List &Int_EFP_Device_Type_List
	Selection	0x0000,	"No Device"
	Selection	0x68C6, "Integrated DisplayPort Only"
	Selection	0x60D6, "Integrated DisplayPort with HDMI/DVI Compatible"
	Selection	0x68D6, "Integrated DisplayPort with DVI Compatible"
	Selection	0x60D2, "Integrated HDMI/DVI"
	Selection	0x68D2, "Integrated DVI Only"
EndList

List &Disabled_Enabled_List
	Selection	0,	"Disabled"
	Selection	1,	"Enabled"
EndList

List &Display_Device_List
	Selection	0001h, "CRT"
	Selection	0008h, "LFP"
	Selection	0002h, "TV"
	Selection	0004h, "EFP"
	Selection	0009h, "CRT and LFP on Single Pipe"
	Selection	0005h, "CRT and EFP on Single Pipe"
	Selection	0801h, "CRT and LFP on Dual Pipes"
	Selection	0201h, "CRT and TV on Dual Pipes"
	Selection	0401h, "CRT and EFP on Dual Pipes"
	Selection	0208h, "LFP and TV on Dual Pipes"
	Selection	0408h, "LFP and EFP on Dual Pipes"
	Selection	0204h, "EFP and TV on Dual Pipes"
	Selection	0209h, "CRT and LFP (Pipe 1) and TV (Pipe 2)"
	Selection	0409h, "CRT and LFP (Pipe 1) and EFP (Pipe 2)"
	Selection	0205h, "CRT and EFP (Pipe 1) and TV (Pipe 2)"
	Selection	0805h, "CRT and EFP (Pipe 1) and LFP (Pipe 2)"
	Selection	0000h, "None"
EndList

List &DOS_Boot_Mode_List
        Selection	0x03,	"03h"
        Selection	0x12,	"12h"
        Selection	0x13,	"13h"
       	Selection	0x30,	"30h"
       	Selection	0x32,	"32h"
       	Selection	0x34,	"34h"
       	Selection	0x40,	"40h"
       	Selection	0x41,	"41h"
       	Selection	0x42,	"42h"
       	Selection	0x43,	"43h"
       	Selection	0x44,	"44h"
       	Selection	0x45,	"45h"
       	Selection	0x50,	"50h"
       	Selection	0x52,	"52h"
        Selection	0x54,	"54h"
EndList

List &DVO_Cfg_List
	Selection	0x00,	"None"
	Selection	0x01,	"Single 12-Bit Device on DVO-B"
	Selection	0x02,	"Single 12-Bit Device on DVO-C"
	Selection	0x09, 	"Single 24-Bit Dual Channel(Even/Odd on DVO-B/C)"
	Selection	0x0A,	"Single 24-Bit Dual Channel(Even/Odd on DVO-C/B)"
	Selection	0x11,	"2 Discrete Devices on DVO-B"
	Selection	0x12,	"2 Discrete Devices on DVO-C"
	Selection	0x13,	"2 Discrete Devices (one on B, other on C)"
	Selection	0x19,	"2 12-bit Devices used together as Dual Link (Even/Odd on DVO-B/C)"
	Selection	0x1A,	"2 12-bit Devices used together as Dual Link (Even/Odd on DVO-C/B)"
EndList

List &DVO_Wiring_List
	Selection	0x00,	"N/A"
	Selection	0x01,	"DVO-B only (or the last one on the chain)"
	Selection	0x02,	"DVO-C only (or the last one on the chain)"
	Selection	0x03,	"DVO-B and S/DVO-C (Dual-channel)"
	Selection	0x05,	"DVO-B, chained to another S/DVO-B"
	Selection	0x06,	"DVO-C, chained to another S/DVO-C"
	Selection	0x0D,	"DVO-B, Master - has one or more Slave Devices"
	Selection	0x0E,	"DVO-C, Master - has one or more Slave Devices"
EndList			 

List &DVO_Port_List
	Selection	0x00,	"N/A"
	Selection	0x01,	"DVO_B"
	Selection	0x02,	"DVO_C"
EndList			 

List &Int_EFP_Port_List
	Selection	0x00,	"N/A"
	Selection	0x01,	"HDMI-B"
	Selection	0x02,	"HDMI-C"
	Selection	0x07,	"DisplayPort-B"
	Selection	0x08,	"DisplayPort-C"
;	Selection	0x09,	"DisplayPort-D"
EndList			 

List &Int_EFP_Connector_Info
	Selection	0x00,	"N/A"
	Selection	0x01,	"HDMI Certified"
	Selection	0x02,	"DisplayPort"
	Selection	0x03,	"DVI"
EndList			 

List &Int_DP_AUX_Channel_List
	Selection	0x00,	"N/A"
	Selection	0x10,	"DisplayPort-B AUX Channel"
	Selection	0x20,	"DisplayPort-C AUX Channel"
;	Selection	0x30,	"DisplayPort-D AUX Channel"
EndList			 

	#IF	$Chipset == 2	; For PineView
List &GPIO_Pin_List
	Selection	0x00,	"N/A"
	Selection	0x01,	"I2C GPIO pins"
	Selection	0x02,	"Analog CRT DDC GPIO pins"
	Selection	0x03,	"Integrated LVDS DDC GPIO pins"
EndList			 
	#ELSE
List &GPIO_Pin_List
	Selection	0x00,	"N/A"
	Selection	0x05,	"Integrated HDMI-B DDC GPIO Pins / sDVO I2C GPIO pins"
	Selection	0x04,	"Integrated HDMI-C DDC GPIO Pins"
	Selection	0x01,	"I2C GPIO pins"
	Selection	0x02,	"Analog CRT DDC GPIO pins"
	Selection	0x03,	"Integrated LVDS DDC GPIO pins"
	Selection	0x1D,	"SDVO DDC1 GPIO pins"
	Selection	0x2D,	"SDVO DDC2 GPIO pins"
EndList			 
	#ENDIF		; For Pineview

List &GMBus_Speed_List
	Selection	0x01,	"50 KHz"
	Selection	0x00,	"100 KHz"
	Selection	0x02,	"400 KHz"
	Selection	0x03,	"1 MHz"
EndList			 

List &Enabled_Disabled_List
	Selection	0,	"Enabled"
	Selection	1,	"Disabled"
EndList

      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
List &IntSys_List
	Selection	0x00,	"Disabled"
	Selection	0x01,	"USE INT 15H"
EndList
      #ENDIF	; $Integrated_LVDS == TRUE

      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
List &Inv_Type_List
	Selection	0x00,	"None/External"
	Selection	0x01,	"I2C"
	Selection	0x02,	"PWM"
EndList
      #ENDIF	; $Integrated_LVDS == TRUE

      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
List &Inv_Polarity_List
	Selection	0x00,	"Normal"
	Selection	0x01,	"Inverted"
EndList
      #ENDIF	; $Integrated_LVDS == TRUE

List &IntXXh_List
	Selection	0x00,	"Disabled"
	Selection	0x01,	"Use Interrupt 15h"
EndList

List &LFP_Cfg_List
	Selection	0x01,	"Intel Integrated LVDS"
	Selection	0x02,	"SDVO-LVDS"
EndList

List &LVDS_Channel_List
	Selection	0x00,	"Single Channel"
	Selection	0x01,	"Dual Channel"
EndList

List &INT_LVDS_Channel_List
	Selection	0x00,	"Automatic Selection"
	Selection	0x01,	"Single Channel"
	Selection	0x02,	"Dual Channel"
EndList

List &LVDS_Config_List
	Selection	0x00,	"No Local Flat Panel"
      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
	Selection	0x01,	"Integrated LVDS (LFP Driven by Int-LVDS Encoder)"
      #ENDIF	; $Integrated_LVDS == TRUE
   #IF	$Chipset != 2
	Selection	0x02,	"SDVO LVDS (LFP Driven by SDVO-LVDS Encoder)"	
      #IF	$eDP == 1	; $eDP == TRUE
	Selection	0x03,	"eDP (LFP Driven by Int-DisplayPort Encoder)"
      #ENDIF	; $eDP == TRUE
   #ENDIF       
EndList

List &No_Yes_List
	Selection	0,	"No"
	Selection	1,	"Yes"
EndList

List &Off_On_List
	Selection	0,	"Off"
	Selection	1,	"On"
EndList

List &OS_Driver_List
	Selection	0,	"OS Default Algorithm"
	Selection	1,	"Driver Algorithm"
EndList

List &OS_DriverP_List
	Selection	0,	"OS Default Algorithm"
	Selection	1,	"Driver Persistence Algorithm"
EndList

List &Panel_Color_Depth_List
	Selection	0x00,	"18-bit Color Depth"
	Selection	0x01,	"24-bit Color Depth"
EndList

      #IF	$LVDS_Config == 3 ; eDP == TRUE
List &eDP_Panel_Color_Depth_List
	Selection	0x00,	"18-bit Color Depth"
	Selection	0x01,	"24-bit Color Depth"
	Selection	0x02,	"30-bit Color Depth"
EndList
      #ENDIF	; $LVDS_Config == 3 ; eDP == TRUE

      #IF	$LVDS_Config == 3 ; eDP == TRUE
List &eDP_Link_DataRate_List
	Selection	0x00,	"1.62 Gbps"
	Selection	0x01,	"2.70 Gbps"
EndList

List &eDP_Link_LaneCount_List
	Selection	0x00,	"x1"
	Selection	0x01,	"x2"
	Selection	0x03,	"x4"
EndList

List &eDP_Link_PreEmp_List
	Selection	0x00,	"0 dB"
	Selection	0x01,	"3.5 dB"
	Selection	0x02,	"6 dB"
	Selection	0x02,	"9.5 dB"	
EndList

List &eDP_Link_VSwing_List
	Selection	0x00,	"0.4 V"
	Selection	0x01,	"0.6 V"
	Selection	0x02,	"0.8 V"
	Selection	0x03,	"1.2 V"	
EndList
      #ENDIF	; $LVDS_Config == 3 ; eDP == TRUE
      

List &Panel_Connector_List
	Selection	0x00,	"SPGW"
	Selection	0x01,	"OpenLDI"
EndList

      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE

List &Panel_List
	Selection	0x00,	"PANEL #01"
	Selection	0x01,	"PANEL #02"
	Selection	0x02,	"PANEL #03"
	Selection	0x03,	"PANEL #04"
	Selection	0x04,	"PANEL #05"
	Selection	0x05,	"PANEL #06"
	Selection	0x06,	"PANEL #07"
	Selection	0x07,	"PANEL #08"
	Selection	0x08,	"PANEL #09"
	Selection	0x09,	"PANEL #10"
	Selection	0x0A,	"PANEL #11"
	Selection	0x0B,	"PANEL #12"
	Selection	0x0C,	"PANEL #13"
	Selection	0x0D,	"PANEL #14"
	Selection	0x0E,	"PANEL #15"
	Selection	0x0F,	"PANEL #16"
EndList
      #ENDIF	; $Integrated_LVDS == TRUE


List &Panel_Stretch_List
	Selection	0x00,	"Disable Panel Fitting"
	Selection	0x01,	"Enabled for Text Modes Only"
	Selection	0x02,	"Enabled for Graphics Modes Only"
	Selection	0x03,	"Enabled for Both Text and Graphics Modes"
EndList

List &PCI_BIOS_Disabled_Enabled_List
	Selection	0x00,	"Disabled"
	Selection	0x01,	"Resize to 0.5K boundary"
	Selection	0x20,	"Resize to 16K boundary"
EndList

List &RelStage
	Selection	1,	"Production"
	Selection	254,	"Evaluation"
EndList

List &Power_Scheme_List
	Selection	0,	"CUI"
	Selection	1,	"3rd Party Application"
EndList

List &Render_Freq_List
	Selection	0,	"High Frequency"
	Selection	1,	"Low Frequency"
EndList

      #IF	$Integrated_LVDS == 1	|| 	$Integrated_EFP == 1; $Integrated_LVDS == TRUE Or Integrated_EFP == TRUE
List &SSC_List
	Selection	0,	"96 MHz"
	Selection	1,	"100 MHz"
EndList
      #ENDIF	; $Integrated_LVDS == TRUE

List &SDVO_Panel_List
	Selection	0x00,	"PANEL #01"
	Selection	0x01,	"PANEL #02"
	Selection	0x02,	"PANEL #03"
	Selection	0x03,	"PANEL #04"
EndList

List &Yes_No_List
	Selection	0,	"Yes"
	Selection	1,	"No"
EndList

List &Sprite_Display_List
	Selection	0,	"Secondary Display"
	Selection	1,	"Primary Display"
EndList

List &Under_Over_List
	Selection	0x0,	"Enable Underscan and Overscan modes"
	Selection	0x1,	"Enable only overscan modes"
	Selection	0x2,	"Enable only underscan modes"
EndList

List &Inter_Exter_List
	Selection	0,	"External Termination"
	Selection	1,	"Internal Termination"
EndList

List &DPS_Panel_Type_List
        Selection       0x00,    "Static DRRS"
        Selection       0x01,    "D2PO"
        Selection       0x02,    "Seamless"
EndList
;==============================================================================
; Page Definitions
;------------------------------------------------------------------------------

BeginInfoBlock
	PPVer	"2.01"
	Image EOF Thru EOF At EOF
EndInfoBlock


;==============================================================================
; Page - Revision History
;------------------------------------------------------------------------------

Page "Revision History "

;	Title	"The Format for the Item in Revision History:" 
; 
;	Title	" DD-MM-YY:  Describe the BMP feature revisions. To allow revision" 
;	Title	"            notes to be seen with smaller display modes, the length"
;	Title	"            of each line must be restricted to the length of the"
;	Title	"            dashed line below. The key words [Add] [Delet] [Update]" 
;	Title	"            have to be used in the description."
;

;	Title	"The List of Revision History:"
;
;	Title	"|------------- Maximum Length of revision note. --------------------|"

	Title   " 28-11-08:  Added Pineview Support." 
	Title   " 06-08-08:  Added DPS_Panel_Type field in Block #40 to distinguish between SDRRS and DRRS panels."
	Title   " 05-12-08:  Added the support for SDVO HDMI selection."
	Title   " 07-18-07:  Added the support for removing Progressive Scan Mode from TV device."
	Title   " 07-18-07:  Added a customized VBT version."
	Title   " 03-07-06:  Added option for each Integrated LVDS panel for setting Panel Channel Type when EDID is enabled."
	Title	" 08-16-05:  Added option to enable/disable integrated CRT/TV Support."
	Title	" 10-28-04:  Added the TV options group."
	Title	" 08-25-09:  Removed CRT Hotplug enable/disable option."
	Title	" 07-21-04:  Added SDVO device power down option."
	Title	" 07-21-04:  Added maintain aspect ratio option."
	Title	" 08-03-04:  Removed Legacy CRT Detect Option. "
	Title	" 07-21-04:  Moved VBIOS Release Stage option to Test Page1. "
	Title	"	     Removed BMP Dual Link Support Options. "
	Title	"	     Cleaned up the text help for BMP options. "
	Title	" 03-15-04:  Added Ambient Light Sense support."
	Title	" 03-15-04:  Added I2C inverter support and group all Power "
	Title	"            Conservation features such as Render Clock Frequency "
	Title	"            switching under driver features according to RCR 236382."
	Title	" 09-12-03:  Added INT 15h, 5f14h hooks support"
	Title	" 09-11-03:  Added bit for NT 4.0 Dual Display Clone Support"
	Title	"            according to RCR 231882."
	Title	" 09-08-03:  Added 6 OEM customizable modes support and GTF Fall "
	Title	"            Back Method BMP bit according to RCR 231968."
	Title	" 08-07-03:  Updated the BMP text to help with feature understanding "
	Title	"            according to RCR 232716."
	Title	" 08-06-03:  Add PC Release setting in Test Page 1. This "
	Title	"            feature allows testing different PC releases."
	Title	" 05-27-03:  Split 'BIOS Features' into 'General Features' and "
	Title	"            'General Video BIOS Features'.  Boot and flag register "
	Title	"            tables where moved to 'Test Page 2'. "
	Title	" 04-10-03:  Add bit for GTF mode removal feature for non-GTF display"
	Title	"            device."
      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
	Title	" 03-15-03:  Remove BIA/BLC option and INT 15h BIA/BLC, and "
	Title	"            local memory hooks."
      #ENDIF	; $Integrated_LVDS == TRUE
	Title	" 11-05-02:  Add bit to disable legacy CRT detect when overlay is "
	Title	"            active."
	Title	" 09-25-02:  Add bit to disable SmoothVision option during VBIOS mode "
	Title	"            sets."
	Title	" 08-22-02:  Fully support OEM customizable mode for both VBIOS and"
	Title	"            driver."
	Title	" 08-01-02:  Remove source image register and extended"
	Title   "            timing registers from OEM customizable mode."
	Title	" 06-19-02:  Add After VESA PM INT 15h, 5F48h hook and"
	Title   "            SMI callback function 13."
	Title	" 04-16-02:  Add Configuration Removal Table to allow the removal of"
	Title   "            specific display combinations."
	Title	" 04-16-02:  Update enable Rotation feature by default."
	Title	" 04-10-02:  Add option to enable/disable the driver rotation feature"
	Title	"            via the VBT table."
	Title	" 03-05-02:  Add revision history page in BMP to list all the changes"
	Title	"            for BMP features."

EndPage


;==============================================================================
; Page - Message Options
;------------------------------------------------------------------------------

Page "Message Options "

	Title	"This BMP Script is used for:" 
	Title	"	Video BIOS Build:  1907"
	Title	"	Video BIOS Baseline:  PC14.8"
	Title	"	BMP Application Version:  PC1.5"

	Title	"Five lines of signon message, maximum of 155 characters"

	MultiText $Signon, "  Video BIOS 'signon' message:", 
	Help	"This feature defines the signon message that will be "
		"displayed at the end of video BIOS POST. when the machine is "
		"booted.  You may enter a maximum of five lines of text, with "
		"no more than 70 characters on each line, and no more than "
		"155 total characters."

	Title	"Display Options"

	Combo	$Msg_Enable, "  Enable signon messages:", &No_Yes_List,
	Help	"'YES' will enable the signon message, copyright message, "
		"eval message, and requested delay.\r\n"
		"\r\n"
		"'NO' will disable showing of the signon messages."

	Combo	$Cls_After_Signon, "  Clear screen after signon:", &Cls_After_Signon_List,
	Help	"This feature allows a selectable option to clear display "
		"after video BIOS signon or leave the signon on the display."
		"\r\n"
		"\r\n"
		"Setting this field to anything other than 'No CLS' will "
		"cause the video BIOS to pause for the specified number of "
		"seconds while displaying the signon and copyright messages."
		"\r\n"
		"The default is 'No CLS', which causes the BIOS to display "
		"the signon messages and continue without pausing or clearing "
		"the screen."

        
EndPage


;==============================================================================
; Page - General Features
;------------------------------------------------------------------------------

Page "General Features"

	Title	"Display Features"

	Combo	$CRT_DDC_GMBUS_Pin, "  Analogue CRT DDC GPIO pin pair:", &GPIO_Pin_List,
	Help	"This feature allows users to select I2C pin pair to access Analogue DDC. \r\n"
		"Following is default Pin Pair map suggested by Intel.  OEMs should select "
		"appropriate Pin Pair if they remap these functions onto other pins.\r\n"
		"\r\n"
		"\r\n"
		"GMBUS Port#	Functions\r\n"
		"  0		Analogue CRT DDC\r\n"
		"  1		SSC clock access\r\n"
		"  2		Integrated LVDS DCC\r\n"
		"  4		SDVO Registers/DDC/SPD\r\n"

      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
	Combo	$LFP_DDC_GMBUS_Pin, "  LFP DDC GPIO pin pair:", &GPIO_Pin_List,
	Help	"This feature allows users to select I2C pin pair to access Integrated LVDS DDC. \r\n"
		"Following is default Pin Pair map suggested by Intel.  OEMs should select "
		"appropriate Pin Pair if they remap these functions onto other pins.\r\n"
		"\r\n"
		"\r\n"
		"GMBUS Port#	Functions\r\n"
		"  0		Analogue CRT DDC\r\n"
		"  1		SSC clock access\r\n"
		"  2		Integrated LVDS DCC\r\n"
		"  4		SDVO Registers/DDC/SPD\r\n"
      #ENDIF	; $Integrated_LVDS == TRUE

      #IF	$BIOS_Type == 1 ; Mobile
	Combo	$bmp_Display_Detect, "  Display(s) must be attached for switching Hot Key:", &Yes_No_List,
	Help	" This feature is applicable only for MOBILE Platforms "
		"This feature allows a selectable option to determine if "
		"the display device(s) must be attached for BIOS Hot Key display "
		"switches.\r\n"
		"\r\n"
		"If 'No' selected, VBIOS will switch to the next display combination "
		"in toggle list when a display switching hotkey is issued, regardless of"
		"what devices currently attached to the system."
		"\r\n"
		"If 'Yes' selected, VBIOS will switch to the next display combination "
		"only if all the devices in the combination attached to the system.  If "
		"the combination of the attached devices does not match with any device "
		"combination in the toggle list, VBIOS will return failure without any "
		"switching attempt.  The caller should assume that no display change if "
		"failure returned by VBIOS."
      #ENDIF	; $BIOS_Type == 1 ; Mobile

      #IF	$BIOS_Type == 1 ; Mobile
	Combo	$CUIHotK_Static_Display, "  Display must be attached for CUI/Hot Key:", &Yes_No_List,
	Help	"This feature allows a selectable option to determine whether "
		"the display device must be attached for CUI Hot Key.\r\n"
		"\r\n"
		"With the 'No' option the display devices do not have to be "
		"attached when enabling the displays via CUI Devices Pages, "
		"CUI Hot Key.  Note: This feature may cause the user to have "
		"a blank display device due to switching to a display that is "
		"not attached.\r\n"
		"\r\n"
		"With the 'Yes' option the display device must be attached or "
		"the display switch attempt will be blocked.\r\n"
            "Note: This bit is supported only in mobile and does not have any effect "
            "for desktop."
      #ENDIF	; $BIOS_Type == 1 ; Mobile
      
	Combo	$Enable_Panel_Fitting, "  Panel Fitting Initial States:", &Panel_Stretch_List,
	Help	"This feature allows a selectable option for initial panel "
		"fitting states.\r\n"
		"\r\n"
		"Note, this initial state is overridden by the panel fitting "
		"hook (5F34h)."

	#IF	$Chipset != 2
	Combo	$Single_DVI_I, "  Single DVI-I connector for CRT and DVI display: ", &No_Yes_List,
	Help	"This option allows single DVI-I connector to support CRT or "
		"DVI display devices using EDID byte 14 bit 7 to distinguish "
		"between them."
	#ENDIF	; PNV
      						; NOT ($BIOS_Type == 1 && $Chipset >= 8 )
      #IF	$BIOS_Type == 1 ; Mobile	; Mobile
      #IF	$Chipset < 8			; $Chipset < 8
	Title	"Spread Spectrum Clock Features"

	Combo	$Enable_SSC, "  LVDS Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LVDS "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LVDS PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LVDS Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LVDS only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."

	Combo	$SSC_Freq, "  LVDS Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"

	Combo	$Disable_SSC_DDT, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ENDIF	; $Chipset < 8		
      #ENDIF	; $BIOS_Type == 1 ; Mobile

      #IF	$BIOS_Type == 1 && $Chipset >= 8; Mobile and >= CAL
	Combo	$D_Connector, "  D-Connector for Integrated TV-Out:", &Disabled_Enabled_List,
	Help	"This feature allows for the definition of whether a D-Connector "
		"is present for integrated TV-out only.  When this feature is set to 'Enabled', "
		"D-Connector is available on the platform.  When this feature is set to 'Disabled', "
		"D-Connector is not available on the platform."
      #ENDIF	; $BIOS_Type == 1 && $Chipset >= 8; Mobile and >= CAL

	Combo	$Int_CRT_Support, "  Integrated CRT Support:", &Disabled_Enabled_List,
	Help	"This feature when set to 'Enabled' will allow integrated CRT out to operate normally.  "
		"This feature when set to 'Disabled' will completely disable all integrated CRT out "
		"capabilities within the VBIOS and driver."
		
      #IF	$BIOS_Type == 1 && $Chipset != 2 ; Mobile
	Combo	$Int_TV_Support, "  Integrated TV-Out Support:", &Disabled_Enabled_List,
	Help	"This feature when set to 'Enabled' will allow integrated TV out to operate normally.  "
		"This feature when set to 'Disabled' will completely disable all integrated TV out "
		"capabilities within the VBIOS and driver."
      #ENDIF	; $BIOS_Type == 1 ; Mobile

      #IF	$Integrated_EFP == 1
	Combo	$DP_SSC_Enb, "  DisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature allow OEMs to enable/disable SSC for external DisplayPort.  "
		"This feature is valid only the attached DisplayPort panel support SSC "
		"\r\n"
	Combo	$DP_SSC_Freq, "  DisplayPort (External Connectors) Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"This feature allow OEMs to select the SSC frequency.  The selected "
		"must frequency must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
		"This feature is valid only if DisplayPort Spread Spectrum Clock feature is enabled "
		"and the attached DisplayPort panel support SSC\r\n"		
      #ENDIF	; $Integrated_EFP == 1

EndPage


;============================================================================
; Page - General Video BIOS Features
;----------------------------------------------------------------------------

Page "General Video BIOS Features"


	Title	"General Video BIOS Features"

	Combo	$bmp_DOS_Boot_Mode, "  DOS boot mode resolution:", &DOS_Boot_Mode_List,
	Help	"This option selects the mode resolution that will be set "
		"when leaving video BIOS POST verses the standard VGA mode "
		"03h.\r\n"
		"\r\n"
		"Modes:\r\n"
		"  03h - 720 x 400 x text\r\n"
		"  12h - 640 x 480 x 4 bpp\r\n"
		"  13h - 320 x 200 x 8 bpp\r\n"
		"  30h - 640 x 480 x 8 bpp\r\n"
		"  32h - 800 x 600 x 8 bpp\r\n"
		"  34h - 1024 x 768 x 8 bpp\r\n"
		"  41h - 640 x 480 x 16 bpp\r\n"
		"  43h - 800 x 600 x 16 bpp\r\n"
		"  45h - 1024 x 768 x 16 bpp\r\n"
		"  50h - 640 x 480 x 32 bpp\r\n"
		"  52h - 800 x 600 x 32 bpp\r\n"
		"  54h - 1024 x 768 x 32 bpp"

	Combo	$bmp_Resize_PCI_BIOS, "  Resize PCI BIOS:", &PCI_BIOS_Disabled_Enabled_List,
	Help	"This feature, when enabled, will resize the run time video "
		"BIOS using the selected granularity.  Resizing will remove "
		"or add padding (end of video BIOS is set to '0') after the "
		"last line of real code.  In some cases, code that is not "
		"needed for reposting will also be removed.\r\n"
		"\r\n"
		"Note: This is a PCI feature where an option ROM may resize "
		"itself by adjusting the option ROM size byte (at offset "
		"C000h:0002h) during that option ROM's POST execution.  A new "
		"checksum is also calculated."

	Combo	$DPMS_AIM_Bit, "  VESA VBE/PM Affects all Display Devices:", &No_Yes_List,
	Help	"This feature allows the VESA VBE \ PM functions to affect "
		"all displays instead of just the CRT.\r\n"
		"\r\n"
		"Note:  The VESA VBE / PM specification was developed for CRT "
		"only (except for reduced on which is not supported).  This "
		"feature allows the 'on', 'standby', 'suspend', and 'off' "
		"state to affect the other displays in an appropriate as "
		"possible way.  Since the original spec was written for CRT "
		"only activating this feature is not VESA compliant."

			; Do not remove the following. Commented out due to 
			; legal issue.

;	Combo	$DPMS_ACPI_Bit, "  Limit DPMS supported power states:", &No_Yes_List,
;	Help	"Feature to limit DPMS supported states by redefining the "
;		"VESA VBE / PM 'standby' and 'suspend' states to be equal to "
;		"the DPMS 'Off' state (horizontal and vertical syncs off).  "
;		"Since this deviates from the VESA VBE/PM and DPMS specs it "
;		"is not VESA compatible."

      #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
	Combo	$Enable_LFPOn_Override, "  LFP 'on' overridden by Function 5F64h, 08h:", &No_Yes_List,
	Help	"This feature when enabled, LFP can only be set to power state 'ON' "
		"through Intel VBIOS function 5F64h, sub-function 08h.  VESA/PM function 4F10h "
		"(sub-function 01h) or Intel VBIOS function 5F64h, sub-function 00h can not "
		"power 'ON' the LFP."
      #ENDIF	; $Integrated_LVDS == 1	; $Integrated_LVDS == TRUE

			; Do not remove the following. For special application.

;	Combo	$Skip_Boot_CRT_Detect, "  Skip CRT Detect during Boot:", &No_Yes_List,
;	Help	"This feature allows user to skip CRT detection during Boot. "
;		"If yes, VBIOS will allow boot to CRT display even though the CRT "
;		"display is not attached."

      #IF	$Chipset > 8	; $Chipset > Calistoga
	Combo	$Allow_Boot_DVI, "  Allow Boot Display to DVI even if DVI is not attached", &No_Yes_List,
	Help	"When Enabled : this feature allows a DVI display to "
		"successfully be used as a Boot Display Device when not attached.\r\n"
		"If the DVI display is not attached, VBIOS shall boot to the DVI "
		"display device using 640x480@60Hz timings.\r\n"
		"When Disabled : it is required for the DVI display to be attached "
		"in order for it to be used as a Boot Display Device."
      #ENDIF	; $Chipset > 8	; $Chipset > Calistoga

      #IF	$Integrated_LVDS == 1 && ( $Chipset >= 10 || $Chipset == 2)	; Mobile && ( CRL or CTG OR Pineview)
	Combo	$Allow_Aspect_Ratio, "  Preserve Aspect Ratio(DOS)", &Disabled_Enabled_List,
	Help	"When this feature is enabled, the Video BIOS will preserve the aspect ratio. "
		"When this feature is disabled, the Video BIOS will not preserve the aspect"
		"ratio but display the screen in full screen mode.\r\n\r\n"
		"Note: This feature is only used when the Video BIOS is the sole component"
		"driving the display. When the Graphics Driver is loaded, the Graphics Driver"
		"will determine based on other VBT bits as well as the end user selection"
		"in CUI the Aspect settings"
      #ENDIF	; $Integrated_LVDS == 1 && $Chipset >= 10
;      #IF	$Chipset == 8	; $Chipset == Calistoga
       #IF	$Chipset != 2	; Not for Pineview	
	Combo	$Override_VGA_720p, "  Underscan 480p modes using 720p timing", &No_Yes_List,
	Help	"When Enabled : this feature shall use 720p timing for all VGA and 480p modes "
		"if the HDMI display device has support for 720p timing. Otherwise, VBIOS shall "
		"use display preferred timing.\r\n"
       #ENDIF	; Not PineView
;      #ENDIF	; $Chipset == 8	; $Chipset == Calistoga

EndPage


;============================================================================
; Page - General Driver Features
;----------------------------------------------------------------------------

Page "General Driver Features"

	Link "General Features" , "General Features"
	Link "Display Features" , "Display Features"
	Link "Legacy Monitor Mode Limit" , "Legacy Monitor Mode Limit"
      #IF	$BIOS_Type == 1
      #IF	$Chipset != 2	; not Pineview 
	Link "Power Conservation" , "Power Conservation"
      #ENDIF	; Not for Pineview	
      #ENDIF	; Mobile
	Link "Rotation Configuration" , "Rotation Configuration"
	Link "Graphics Mode to Boot on Windows" , "Graphics Mode to Boot on Windows"
      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
	Link "Driver Persistence" , "Driver Persistence"
      #ENDIF	; $BIOS_Type == MOBILE

      #IF	$Chipset != 2	; Not for Pineview
	Link "TV Features" , "TV Features"
      #ENDIF	; Not for Pineview

	Page	"General Features"
		Link	"Close Table" , ".."

	EditNum	$VBT_Customization_Version, "  VBT Customization Version:", DEC,
	Help	"This feature allows the OEM to have a customized VBT version "
		"number. The permissible values for VBT Customization version "
		"is from 0 to 255.\r\n"
		
	Combo	$Driver_Boot_Device, "  First Boot Display Device:", &OS_Driver_List,
	Help	"This feature allows the OEM to select which algorithm to "
		"follow on the first boot after the driver has been "
		"installed.\r\n"
		"\r\n"
		"OS Default - If this is selected, the operating system's "
		"algorithm will be used.\r\n"
		"\r\n"
		"Driver Default - If this is selected, the boot device will "
		"follow the driver algorithm.  The expected behavior can be "
		"found in the Driver PRD chapter:  'First Boot Default "
		"Display Resolutions'."

	Combo	$Block_Disp_Switch, "  Block Display Switch when Overlay is Active:", &No_Yes_List,
	Help	"This feature allows the OEM to disable display switching via "
		"CUI or Hot-Key if an overlay is active.  When set to yes, "
		"any display switching will be blocked when an overlay is "
		"active.  When set to no, display switching will not be "
		"blocked when an overlay is active.\r\n"
		"\r\n"
		"Note: Display switching will not be blocked if the "
		"application utilizing the overlay disables the overlay on "
		"the display switch request."

 	Combo	$Allow_FDOS_Disp_Switch, "  Allow Full Screen DOS Display Switching:", &No_Yes_List,
	Help	"This feature allows display switching when the system is in "
		"full screen DOS.  When set to yes, display switching will be "
		"allowed while system is in full screen DOS.  When set to no, "
		"display switching will be blocked when system is in full "
		"screen DOS."
      #IF	$Chipset != 2	; Not for Pineview 
	Combo	$Hot_Plug_DVO, "  DVO/SDVO Hot Plug:", &Disabled_Enabled_List,
	Help	"This feature allows the OEM to disable the DVO/SDVO Hot Plug "
		"capability."
      #ENDIF	; Not for Pineview

      #IF	$Chipset >= 7 ; $Chipset >= LP-G
	Combo	$Hot_Plug_CRT, "  CRT Hot Plug:", &Disabled_Enabled_List,
	Help	"This feature allows the OEM to disable the CRT Hot Plug "
		"capability."
      #ENDIF	; $Chipset >= LP-G 

      #IF	$Chipset == 8 || $Chipset ==10 || $Chipset ==13
	Combo	$Hot_Plug_TV, "  Integrated TV-Out Hot Plug:", &Disabled_Enabled_List,
	Help	"This feature allows the OEM to disable the Integrated TV-Out Hot Plug "
		"capability."
      #ENDIF	; $Chipset == 8 || $Chipset ==10 || $Chipset ==13

      #IF	$BIOS_Type == 1
	Combo	$Enable_LFP_Primary, "  LFP as Primary Display:", &Disabled_Enabled_List,
	Help	"This feature allows the OEM to set the LFP to be the primary "
		"display at all times.  Note:  If this feature is set to "
		"enable, the end-user will not have the capability to set any "
		"other device as primary in the CUI or the OS properties "
		"page. This feature will only affect an LFP connected via the "
		"integrated LVDS."
      #ENDIF	; ; Mobile

      #IF	$BIOS_Type == 1
	Combo	$Use_110h_for_LFP, "  Use _DOD 00000110h ID for Primary LFP:", &No_Yes_List,
	Help	"This feature when set to yes will use the legacy value "
		"00000110h as the ID for primary LFP in the ACPI _DOD, _DGS "
		"method.  The ID is passed to the system BIOS through INT10h function 5F64h  "
		"The ID 00000110h is the backwards compatible ACPI ID "
		"for LFP, which may be necessary in where Microsoft* WindowsXP "
		"TabletPC*'s Graphical User Interface is required for Backlight "
		"Control(hardcoded by some Windows OSes). In all other cases, "
		"the default new ID is strongly preferred."

      #ENDIF	; Mobile
      
      #IF	$BIOS_Type == 1

			; Please do not remove the following BMP feature.  It
			; is for a special application.

;	Combo	$Drv_Int15_hook, "  Enable/Disable VBIOS/Driver INT15 hook:", &Disabled_Enabled_List,
;	Help	"This option enables or disables VBIOS/Driver INT15 hook."

      #ENDIF	; ; Mobile 

	Combo	$DVD_Sprite_Clone, "  Disable Sprite (DVD) in Clone Mode:", &Yes_No_List,
	Help	"This feature when selected 'No', will allow the sprite to be "
		"active during DVD playback when the platform is in a Dual "
		"Display Clone configuration.  Otherwise, when selected 'Yes', "
		"the overlay sprite will be disabled during DVD playback when the "
		"platform is in a Dual Display Clone configuration."

	Combo	$GTF_Mode_Pruning, "  Selective Mode Pruning:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct driver software not "
		"to enumerate or set specific display modes determined as "
		"unsupported according to the EDID capabilities of the "
		"display. If the display indicates support for all GTF/DMTS "
		"timings in the display's EDID, then all modes supported by "
		"the graphics host will be enumerated.  If the display does "
		"NOT indicate support for GTF/DMTS timings in the display's "
		"EDID, then some modes/timings that may have been enumerated "
		"by the display driver shall not be set."
		"\r\n"
		"\r\n"
		"Note: This option applies for all display types.  And in the "
		"absence of other platform configuration information (e.g. "
		"OEM Customizable Mode) requiring inclusion of that display "
		"mode/timings."

	Combo	$Sprite_Display_Assign, "  Sprite Display Assignment for When Overlay is Active in Clone Mode:", &Sprite_Display_List,
	Help	"This feature when set to Primary Display, the driver will "
		"assign the Sprite (2ndary overlay) to the primary display "
		"defined in the current Dual Display Clone configuration, "
		"otherwise when this feature is set to Secondary Display, the "
		"driver will assign the Sprite (2ndary overlay) to the "
		"secondary display defined in the current Dual Display Clone "
		"configuration. Note:  This bit will have no affect if an "
		"application is using the VMR API. "

      #IF	$Chipset != 2	; Not for Pineview
	Combo	$Enable_Int_Src_Term, "  Enable Internal Source Termination for HDMI:", &Inter_Exter_List,
	Help	"Allows the driver to know to program the HDMI part "
		"to support Internal Source termination mode.\r\n"
      #ENDIF	; Not for Pineview		
	EndPage

	Page	"Display Features"
		Link	"Close Table" , ".."

 	Combo	$CUI_Maintain_Aspect, "  Enable 'Maintain Aspect Ratio':", &No_Yes_List,
	Help	"This feature allows the OEM to enable or disable the 'Maintain "
		"Aspect Ratio' feature.  When the option is set to Yes, the "
		"feature will be enabled and CUI will show for end user "
		"selection 'Maintain Aspect Ratio'.  When the option is set to "
		"No, the complete 'Maintain Aspect Ratio' feature will be disabled."

	Combo	$Preserve_Aspect_Ratio, "  Preserve Aspect Ratio:", &Disabled_Enabled_List,
	Help	"This feature allows the OEM to configure the default option "
		"for aspect ratio settings. When enabled, the CUI will reflect "
		"preserve the aspect ratio as active setting.  Otherwise, when "
		"disabled, the CUI will use the setting 'Panel Fitting Initial "
		"States' as default aspect ratio setting.  This option will "
		"only be available for initial boot value. Any subsequent "
		"change in CUI will have higher priority."
      
	EndPage

	Page	"Legacy Monitor Mode Limit"
		Link	"Close Table" , ".."

	EditNum	$Legacy_Monitor_Max_X, "  Maximum X Resolution (Pixels):", DEC,
	Help	"This feature allows the limiting of selectable display modes "
		"when a legacy monitor is detected.  The maximum resolution is "
		"specified by a maximum number of horizontal active pixels."
		"\r\n"
		"Note: A legacy monitor is defined as a monitor with no DDC "
		"available."

	EditNum	$Legacy_Monitor_Max_Y, "  Maximum Y Resolution (Pixels):", DEC,
	Help	"This feature allows the limiting of selectable display modes "
		"when a legacy monitor is detected.  The maximum resolution is "
		"specified by a maximum number of vertical active pixels."
		"\r\n"
		"Note: A legacy monitor is defined as a monitor with no DDC "
		"available."

	EditNum	$Legacy_Monitor_Max_RR, "  Maximum Refresh Rate (Hz):", DEC,
	Help	"This feature allows the limiting of selectable display modes "
		"when a legacy monitor is detected.  The maximum refresh rate "
		"is specified in Hz."
		"\r\n"
		"Note: A legacy monitor is defined as a monitor with no DDC "
		"available."
	EndPage
	
       #IF	$BIOS_Type == 1
      #IF	$Chipset != 2	; Not for Pineview       
	Page	"Power Conservation"
		Link	"Close Table" , ".."

	Combo	$SDVO_Device_Power_Down, "  SDVO device power down:", &Disabled_Enabled_List,
	Help	"This feature powers down the SDVO device when the system is "
		"running in battery mode (DC) and the corresponding display "
		"not connected."
      #ENDIF	; Not for Pineview

     #IF	($Chipset == 13 || $Chipset == 10 || $Chipset == 8 || $Chipset == 2)
     						; $Chipset == (CTG || CRL || CAL)
						; DISABLE_DFGT
     #ELSE	; $Chipset == 13 || $Chipset == 10 || $Chipset == 8
	Combo	$Render_Freq_Switch, "  Enable Intel® Dual-Frequency Graphics Technology:", &No_Yes_List,
	Help	"This feature determines whether the Intel® Dual-Frequency "
		"Graphics Technology (DFGT) is enabled or disabled.  Intel® "
		"DFGT is a graphics power savings technology that adaptively "
		"lowers the render clock frequency when the system is running "
		"in battery mode.  Note that this technology is only active "
		"when the system is running in battery mode and the LFP is the "
		"only active display device. When Intel® DFGT is enabled, the "
		"Default Render Clock Frequency should also be selected."
      
	Combo	$Render_Freq_Default, "  Default Render Clock Frequency:", &Render_Freq_List,
	Help	"This feature allows the OEM to set the default render clock "
		"frequency when the Intel® Dual-Frequency Graphics Technology "
		"feature is enabled.\r\n"
		"\r\n"
		"Note: This is the default option the end-user will see when "
		"the CUI is opened."
      #ENDIF	; $Chipset == 13 || $Chipset == 10 || $Chipset == 8

      #IF	$Chipset != 2	; Not for Pineview   
	Combo	$BIA_Enable, "  Intel® Display Power Saving Technology Support for the LFP:", &Disabled_Enabled_List,
	Help	"This feature determines whether the Intel® Display Power "
		"Savings Technology (DPST) is enabled or disabled.  Intel® DPST "
		"is a display power savings technology that changes the "
		"intensity of colors in order to conserve backlight power."
		"\r\n\r\nNote: This technology is only active when the system "
		"is running in battery mode and the LFP is the only active "
		"display device."

	Combo	$BIA_Aggress_Level, "  Power Conservation Preference Level for the LFP:", &Pwr_Pref_List,
	Help	"This feature defines the Intel® Display Power Saving Technology "
		"aggressiveness level if and only if the feature Intel® Display Power Saving "
		"Technology is enabled."   
		"\r\n\r\nThe following are the definitions for each level:"
		"\r\n1 - Maximum Quality - shall use no DPST "
		"\r\n2 - Provides  the user the maximum "
		"brightness for their embedded Local Flat Panel (LFP)while DPST is in use"
		"\r\n3 - This level defines maximum amount of brightness with "
		"minimal power savings"
		"\r\n4 - This level defines an intermediate value for brightness amount"
		"\r\n5 - This level defines an intermediate value for the brightness amount"
		"\r\n6 - Maximum Battery - Provided the user with the minimum amount of "
		"brightness capable for their LFP with the maximum power savings"

	Combo	$ALS_Enable, "  Intel® Automatic Display Brightness Support for the LFP:", &Disabled_Enabled_List,
	Help	"This feature determines whether Intel® Automatic Display Brightness is to be "
		"enabled.  Intel® Automatic Display Brightness adjusts the brightness of the "
		"embedded Local Flat Panel (LFP) depending on the current "
		"ambient light environment.  When enabled, the driver and VBIOS"
		" will control the backlight brightness of the LFP depending "
		"on the ambient environment if and only if the LFP is the only "
		"active display.  When disabled, the driver and VBIOS will "
		"perform no action."

	Link "Ambient Light Response Data" , "Ambient Light Response Data"

		Page	"Ambient Light Response Data"
			Link	"Close Table" , ".."

			Table	$ALS_Response_Data " Ambient Light Response Data",
			Column	"Backlight Adjust", 2 bytes, EHEX
			Column	"Lux", 2 bytes, EHEX,
			Help	"This feature defines values used to calibrate the "
				"Intel® Automatic Display Brightness policy's "
				"response to account for specific hardware implementation "
				"details such as sensor placement and optics.  Up to five "
				"points can be specified, where each point indicates a given "
				"ambient light illuminance to display luminance mapping "
				"specified as (<%BacklightAdjust>, <Lux>).  Points should be "
				"listed in monotonically increasing order by ambient light "
				"illuminance (lux).  A minimum of two points are required "
				"(min and max)."
		EndPage
	EndPage
     #ENDIF	; not Pineview 	
     #ENDIF	; Mobile
	
	Page	"Rotation Configuration"
		Link	"Close Table" , ".."
	
	Combo	$Rot_Enable, "  Enable Rotation:", &No_Yes_List,
	Help	"This feature when set to yes, will allow for rotation.  "
		"Otherwise, when the feature is set to no, the rotation "
		"functionality will be disabled within the driver."

	EditNum	$Rot_Flags, "  Rotation Flags (Binary):", BIN,
	Help	"Enter bitfield for rotation configuration."
	EndPage
	
	Page	"Graphics Mode to Boot on Windows"
		Link	"Close Table" , ".."

	EditNum	$Driver_Boot_Mode_X, "  X Resolution (Pixels):", DEC,
	Help	"This feature allows the OEM to select which resolution the "
		"system will use on the first reboot after the driver has "
		"been installed.\r\n"
		"\r\n"
		"X Resolution (Pixels)\r\n"
		"\r\n"
		"Note: This feature is only used when the Boot Display "
		"Algorithm is set to Driver Default."

	EditNum	$Driver_Boot_Mode_Y, "  Y Resolution (Pixels):", DEC,
	Help	"This feature allows the OEM to select which resolution the "
		"system will use on the first reboot after the driver has "
		"been installed.\r\n"
		"\r\n"
		"Y Resolution (Pixels)\r\n"
		"\r\n"
		"Note: This feature is only used when the Boot Display "
		"Algorithm is set to Driver Default."

	EditNum	$Driver_Boot_Mode_BPP, "  Color Depth (Bits/Pixel):", DEC,
	Help	"This feature allows the OEM to select which resolution the "
		"system will use on the first reboot after the driver has "
		"been installed.\r\n"
		"\r\n"
		"Color Depth (BPP)\r\n"
		"\r\n"
		"Note: This feature is only used when the Boot Display "
		"Algorithm is set to Driver Default."

	EditNum	$Driver_Boot_Mode_RR, "  Refresh Rate (Hz):", DEC,
	Help	"This feature allows the OEM to select which resolution the "
		"system will use on the first reboot after the driver has "
		"been installed.\r\n"
		"\r\n"
		"Refresh Rate (Hz)\r\n"
		"\r\n"
		"Note: This feature is only used when the Boot Display "
		"Algorithm is set to Driver Default."
	EndPage
	
      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
	Page	"Driver Persistence"
		Link	"Close Table" , ".."
      #ENDIF	; $BIOS_Type == MOBILE

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
	Combo	$Driver_Persist_PM, "  Mode Persistence on a Power Management Event:", &OS_DriverP_List,
	Help	"This feature allows mode persistence to be enabled on a "
		"power management event.\r\n"
		"\r\n"
		"If mode persistence is disabled, the OS Default Algorithm "
		"will be applied.\r\n"
		"\r\n"
		"If mode persistence is enabled, the Driver Algorithm will be "
		"used and the appropriate Display Configuration will be "
		"applied for the current State.\r\n"
		"\r\n"
		"Note: State refers to the attached devices (or lack of "
		"devices) as well as the display configuration (resolution, "
		"refresh rate and color depth for each device as well as the "
		"multi-display configuration information)."
			 
	Combo	$Driver_Persist_Lid_Switch, "  Mode Persistence on a  Lid Switch event:", &OS_DriverP_List,
	Help	" This feature is applicable only for MOBILE Platforms "
		"This feature allows mode persistence to be enabled on a "
		"Lid Switch event.\r\n"
		"\r\n"
		"If mode persistence is disabled, the OS Default Algorithm "
		"will be applied.\r\n"
		"\r\n"
		"If mode persistence is enabled, the Driver Algorithm will be "
		"used and the appropriate Display Configuration will be "
		"applied for the current State.\r\n"
		"\r\n"
		"Note: State refers to the attached devices (or lack of "
		"devices) as well as the display configuration (resolution, "
		"refresh rate and color depth for each device as well as the "
		"multi-display configuration information)."

	Combo	$Driver_Persist_Hotkey, "  Mode Persistence on a  Hot Key Event:", &OS_DriverP_List,
	Help	" This feature is applicable only for MOBILE Platforms "
		"This feature allows mode persistence to be enabled on a Hot "
		"Key event.\r\n"
		"\r\n"
		"If mode persistence is disabled, the OS Default Algorithm "
		"will be applied.\r\n"
		"\r\n"
		"If mode persistence is enabled, the Driver Algorithm will "
		"be used and the appropriate Display Configuration will be "
		"applied for the current State.\r\n"
		"\r\n"
		"Note:  State refers to the attached devices (or lack of "
		"devices) as well as the display configuration (resolution, "
		"refresh rate and color depth for each device as well as the "
		"multi-display configuration information)."

       #IF	$Chipset != 2		; not Supported in Pineview    	
	Combo	$Driver_Persist_Docking, "  Mode Persistence on a Dock/Undock event:", &OS_DriverP_List,
	Help	"This feature allows mode persistence to be enabled on a "
		"Dock/Undock event.\r\n"
		"\r\n"
		"If mode persistence is disabled, the OS Default Algorithm "
		"will be applied.\r\n"
		"\r\n"
		"If mode persistence is enabled, the Driver Algorithm will "
		"be used and the appropriate Display Configuration will be "
		"applied for the current State.\r\n"
		"\r\n"
		"Note: State refers to the attached devices (or lack of "
		"devices) as well as the display configuration (resolution, "
		"refresh rate and color depth for each device as well as the "
		"multi-display configuration information).\r\n"
       #ENDIF	; not Supported in Pineview

	Combo	$PersistHotkeyRestoreCloneMDS, "  On Hot-Key Event enable MDS/ Dual Display Clone:", &No_Yes_List,
	Help	" This feature is applicable only for MOBILE Platforms "
		"This feature allows the OEM to determine if the system "
		"should go into extended desktop on a Hot-Key persistence "
		"event.\r\n"
		"\r\n"
		"If No, extended desktop will be saved/applied.\r\n"
		"\r\n"
		"If Yes, extended desktop will not be saved/applied.  "
		"Instead, Dual Display Clone will be utilized.\r\n"
		"\r\n"
		"This feature can only be used if the OEM has enabled mode "
		"persistence on a hot-key event."

	Combo	$PersistHotkeyRestoreRefreshrate, "  On Hot Key Event, Save Refresh Rate:", &No_Yes_List,
	Help	" This feature is applicable only for MOBILE Platforms "
		"This feature allows the OEM to determine if the Refresh Rate "
		"should be saved/applied on a hot-key event.\r\n"
		"\r\n"
		"This feature can only be used if mode persistence has been "
		"enabled on a hot-key event."

	Combo	$PersistHotkeyRestorePipe, "  On Hot Key Event, Save Pipe Configuration Information:", &No_Yes_List,
	Help	" This feature is applicable only for MOBILE Platforms "
		"This feature allows the OEM to determine if the Pipe "
		"Configuration information should be saved/applied on a "
		"hot-key event.\r\n"
		"\r\n"
		"This feature can only be used if mode persistence has been "
		"enabled on a hot-key event."

	Combo	$PersistHotkeyRestoreMode, "  For Hot Key Persistence on Restore Mode:", &No_Yes_List,
	Help	" This feature is applicable only for MOBILE Platforms "
		"This feature allows the OEM to determine if the Mode "
		"information should be saved/applied on a hot-key event.\r\n"
		"\r\n"
		"This feature can only be used if mode persistence has been "
		"enabled on a hot-key event."
      #ENDIF	; $BIOS_Type == MOBILE

      #IF	$BIOS_Type == 1 ; Mobile
  	Combo	$PersistEDIDRestoreMode, "  Enable EDID Persistence for Restore Mode:", &No_Yes_List,
	Help	"This option allows the OEM to utilize information from the "
		"EDID of a device when a mode persistence event occurs.\r\n"
		"\r\n"
		"Note: This feature can only be used if mode persistence has "
		"been enabled on hotkey / lid switch / power persistence."
  
	Combo	$PersistHotPlugRestoreMode, "  Hot Plug Persistence on Restore Mode:", &No_Yes_List,
	Help	"This feature allows mode persistence to be enabled when a "
		"any display device is Hot-Plugged into the system.\r\n"
		"\r\n"
		"If NO is selected, the device will still appear in the "
		"properties pages (OS and CUI), but the current display "
		"configuration will not change.\r\n"
		"\r\n"
		"If YES is selected, hot-plug persistence will restore the "
		"last known state prior to the disconnection of the display "
		"device."

      #IF	$Chipset == 8  ;If $Chipset == CAL
	Combo	$PersistCRTHotplugRestoreMode, "  CRT Hotplug/unplug Presistence on Restore Mode:", &No_Yes_List,
	Help	"This feature allows mode persistence to be enabled when a "
		"CRT device is Hot-Plugged or unplugged from the system.\r\n"
		"\r\n"
		"If the VBT for CRT hotplug is selected to disable, this "
		"CRT hotplug persistence bit will be ignored.\r\n "
		"\r\n"
		"If No is selected, the device will still appear in the property "
		"pages(OS and CUI), but the graphics will not save the current display "
		"configureation state upon a hotplug or unplug event.\r\n"
		"\r\n"
		"If Yes is selected, hotplug persistence will restore the last known "
		"state prior to the last disconnection of the CRT device."
      #ENDIF    ; $Chipset == 8

	EditNum	$PersistMaxConfig, "  Maximum # of Persistence States:", DEC,
	Help	"This feature allows the OEM to determine the number of "
		"configuration States to be saved by the registry.  The "
		"selectable range is from 10-200.\r\n"
		"\r\n"
		"Note: This feature can only be used when 'Enable EDID "
		"persistence for Restore Mode' is selected."
      #ENDIF	; Mobile
      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
	EndPage
      #ENDIF	; $BIOS_Type == MOBILE

      #IF	$Chipset != 2	; Not for Pineview
	Page	"TV Features"
		Link	"Close Table" , ".."

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
	Combo	$Under_Over_Scan_Via_YPrPb, "  Enable underscanned modes for HDTV via Component (YPrPb):", &Under_Over_List,
	Help	"For 720p format when enable underscan and overscan modes "
		"option is selected, expose 1184x666 and 1280x720 through CUI"
		"\r\n"
		"For 1080i format when enable underscan and overscan modes "
		"option is selected, expose 1776x1080 and 1920x1080 through CUI"
      #ENDIF	; $BIOS_Type == MOBILE

	Combo	$Under_Over_Scan_Via_DVI, "  Enable underscanned modes for HDTV via DVI:", &Under_Over_List,
	Help	"When 720p is found in the EDID structure of the active DVI "
		"display and enable underscan modes is selected, 1184x666 will "
		"be available and be centered in 720p timings when enabled. "
		"\r\n"
		"When 1080i or 1080p is found in the EDID structure of the "
		"active DVI display and enable underscan modes is selected, "
		"1776x1000 will be centered in appropriate 1080 timings. "

	Title	"\r\n"
	Title	"  Add 1776x1000 when 1080i is selected and add 1184x666 when 720p is selected for HDTV via DVI:"
	Combo	$Add_Overscan_Mode, " ", &Disabled_Enabled_List,
	Help	"For 1080i format, 1776x1000 will be made available in CUI "
		"along with native resolution 1920x1080.  For 720p format, "
		"1184x666 will be made available in CUI along with native "
		"resolution 1280x720. These resolutions are exposed to get the "
		"TV image under scanned with task bar visible."

	EndPage
      #ENDIF	; Not for Pineview
EndPage

;==============================================================================
; Page - Boot Display Algorithm
;------------------------------------------------------------------------------

Page "Boot Display Algorithm "

	Table	$Dev_Boot_Table " Display Device Boot Table",
		Column "Devices Attached" , 1 byte , BIN
		Column "Devices to Boot" , 1 byte , BIN, 
	Help	"This feature allows a configurable table for video BIOS POST "
		"boot up display device.\r\n"
		"\r\n"
		"If the displays in the 'Devices Attached' column are "
		"detected, the video BIOS will boot to the display "
		"combination in the 'Devices to Boot' column.  The bit "
		"pattern for either column is as follows:\r\n" 
		"\r\n"
		"   Bit: 7     6     5     4     3     2     1    0 \r\n"
		"        LFP2  EFP2  TV2  CRT2   LFP   EFP   TV   CRT \r\n"
		"\r\n"
		"Some examples:\r\n"
		"\tDB 00000001b,\t00000001b\t; CRT only    -> CRT \r\n"
		"\tDB 00000011b,\t00000001b\t; CRT+TV      -> CRT \r\n"
		"\tDB 00001101b,\t00000101b\t; LFP+CRT+EFP -> CRT+EFP \r\n"
		"\tDB 00001011b,\t00000001b\t; LFP+CRT+TV  -> CRT \r\n"
		"\r\n"
		"Set both columns of a row equal zero to remove it from the "
		"list.\r\n"
		"\r\n"
		"Note, This table is skipped when a valid display "
		"combination is returned by the 5F35h (Boot Display) system "
		"BIOS hook."

EndPage


      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
;==============================================================================
; Page - Display Device Toggle Lists
;------------------------------------------------------------------------------

Page "Display Device Toggle Lists"

	Link "Toggle/Capabilities List 1" , "Display Toggle List 1"
	Link "Toggle/Capabilities List 2" , "Display Toggle List 2"
	Link "Toggle/Capabilities List 3" , "Display Toggle List 3"
	Link "Toggle/Capabilities List 4" , "Display Toggle List 4"

	Page "Display Toggle List 1"

		Link	"Close Table" , ".."

		Table	$Toggle_List1 "Display Toggle List 1",
			Column "Display Select", 2 bytes, EHEX
			Column "Reserved", 1 byte, DEC,
		Help	"This feature is applicable only for MOBILE Platforms "
			"These toggle lists are used by the video BIOS and "
			"device drivers to help support the system BIOS with "
			"switch display device Hot Keys.  The basic algorithm "
			"in the current display is found on the list and the "
			"next settable display combination is set.  If no "
			"settable display combinations are found the function "
			"returns fail.\r\n"
			"\r\n"
			"The video BIOS will 'OR' the bits of the two pipes "
			"together to create a single pipe display device.  "
			"The Intel developed drivers will use the display "
			"lists as they are.  The divers also use this list to "
			"get pipe information for ACPI switch display device "
			"Hot Keys. Four lists are given to allow for multiple "
			"Hot Keys or creative solutions.\r\n"
			"\r\n"
			"Display Select (Refer to VBIOS HLD for valid "
			"selections):\r\n"
			"\r\n"
			"\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n"
			"\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
			"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT"

	EndPage

	Page "Display Toggle List 2"

		Link	"Close Table" , ".."

		Table	$Toggle_List2 "Display Toggle List 2",
			Column "Display Select", 2 bytes, EHEX
			Column "Reserved", 1 byte, DEC,
		Help	"This feature is applicable only for MOBILE Platforms "
			"These toggle lists are used by the video BIOS and "
			"device drivers to help support the system BIOS with "
			"switch display device Hot Keys.  The basic algorithm "
			"in the current display is found on the list and the "
			"next settable display combination is set.  If no "
			"settable display combinations are found the function "
			"returns fail.\r\n"
			"\r\n"
			"The video BIOS will 'OR' the bits of the two pipes "
			"together to create a single pipe display device.  "
			"The Intel developed drivers will use the display "
			"lists as they are.  The divers also use this list to "
			"get pipe information for ACPI switch display device "
			"Hot Keys. Four lists are given to allow for multiple "
			"Hot Keys or creative solutions.\r\n"
			"\r\n"
			"Display Select (Refer to VBIOS HLD for valid "
			"selections):\r\n"
			"\r\n"
			"\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n"
			"\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
			"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT"

	EndPage

	Page "Display Toggle List 3"

		Link	"Close Table" , ".."

		Table	$Toggle_List3 "Display Toggle List 3",
			Column "Display Select", 2 bytes, EHEX
			Column "Reserved", 1 byte, DEC,
		Help	"This feature is applicable only for MOBILE Platforms "
			"These toggle lists are used by the video BIOS and "
			"device drivers to help support the system BIOS with "
			"switch display device Hot Keys.  The basic algorithm "
			"in the current display is found on the list and the "
			"next settable display combination is set.  If no "
			"settable display combinations are found the function "
			"returns fail.\r\n"
			"\r\n"
			"The video BIOS will 'OR' the bits of the two pipes "
			"together to create a single pipe display device.  "
			"The Intel developed drivers will use the display "
			"lists as they are.  The divers also use this list to "
			"get pipe information for ACPI switch display device "
			"Hot Keys. Four lists are given to allow for multiple "
			"Hot Keys or creative solutions.\r\n"
			"\r\n"
			"Display Select (Refer to VBIOS HLD for valid "
			"selections):\r\n"
			"\r\n"
			"\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n"
			"\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
			"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT"

	EndPage

	Page "Display Toggle List 4"

		Link	"Close Table" , ".."

		Table	$Toggle_List4 "Display Toggle List 4",
			Column "Display Select", 2 bytes, EHEX
			Column "Reserved", 1 byte, DEC,
		Help	"This feature is applicable only for MOBILE Platforms "
			"These toggle lists are used by the video BIOS and "
			"device drivers to help support the system BIOS with "
			"switch display device Hot Keys.  The basic algorithm "
			"in the current display is found on the list and the "
			"next settable display combination is set.  If no "
			"settable display combinations are found the function "
			"returns fail.\r\n"
			"\r\n"
			"The video BIOS will 'OR' the bits of the two pipes "
			"together to create a single pipe display device.  "
			"The Intel developed drivers will use the display "
			"lists as they are.  The divers also use this list to "
			"get pipe information for ACPI switch display device "
			"Hot Keys. Four lists are given to allow for multiple "
			"Hot Keys or creative solutions.\r\n"
			"\r\n"
			"Display Select (Refer to VBIOS HLD for valid "
			"selections):\r\n"
			"\r\n"
			"\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n"
			"\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
			"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT"

	EndPage

EndPage
      #ENDIF	; $BIOS_Type == MOBILE


;==============================================================================
; Page - System BIOS Hooks
;------------------------------------------------------------------------------

Page "System BIOS Hooks "

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE

			; Do not remove.  For special application.
			
;	Combo	$H14_Update_Display, "5F14h - Update Expansion/Display State:", &IntXXh_List, 
;	Help	"When this feature is enabled (Use Interrupt 15h), the video "
;		"BIOS will call the interrupt 15h, 5F14h, 078Dh hook, as specified "
;		"in the video BIOS reference guide, at the end of video BIOS "
;		"POST.  When disabled, 5F14h, 078Dh will not be called."

	Combo	$H14_Get_Misc_Status, "5F14h - Get Miscellaneous Status:", &IntXXh_List, 
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F14h, 078Fh hook, as specified "
		"in the video BIOS reference guide, at the end of video BIOS "
		"POST.  When disabled, 5F14h, 078Fh will not be called."

	Combo	$H31_POST_End_Hook, "5F31h - POST Completion Hook:", &IntXXh_List, 
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F31h hook, as specified "
		"in the video BIOS reference guide, at the end of video BIOS "
		"POST.  When disabled, 5F31h will not be called."

	Combo	$H33_After_Mode_Set, "5F33h - Hook After Mode Set:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F33h hook, as specified "
		"in the video BIOS reference guide, at the end of set mode.  "
		"When disabled, 5F33h will not be called."

	Combo	$H34_Set_LFP_Fitting, "5F34h - Set Panel Fitting Hook:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F34h hook ,as specified "
		"in the video BIOS reference guide, in the middle of video "
		"BIOS POST.  The returned value will override the default BMP "
		"setting.  When disabled, 5F34h will not be called."

	Combo	$H35_Bootup_Display, "5F35h - Boot Up Display Devices Hook:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F35h hook, as specified "
		"in the video BIOS reference guide, in the middle of video "
		"BIOS POST.  When disabled, 5F35h will not be called.\r\n"
		"\r\n"
		"Note, Enabling this hook and returning a good display"
		"combination will override the 'Boot Display Algorithm' "
		"table."
      #IF	$Chipset != 2	; Not for Pineview
	Combo	$H36_Boot_TV_Format, "5F36h - Boot TV Format Hook:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F36h hook, as specified "
		"in the video BIOS reference guide, in the middle of video "
		"BIOS POST.  When disabled, 5F36h will not be called."
      #ENDIF	; Not for Pineview
	Combo	$H38_Before_Mode_Set, "5F38h - Hook Before Mode Set:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F38h hook, as specified "
		"in the video BIOS reference guide, at the beginning of set "
		"mode.  When disabled, 5F38h will not be called."

	Combo	$H40_Set_Panel_Type, "5F40h - Panel Type Hook:", &IntXXh_List,
	Help	"This feature when enabled (Use interrupt 15h) allows the "
		"system BIOS to return the panel type to be used in booting "
		"the system and from then on by both the video BIOS and "
		"driver.  If disabled, the BMPed panel type will be used."

	Combo	$H45_VESA_DDC_Hook, "5F45h - Hook Before VESA VBE/DDC:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F45h hook, as specified "
		"in the video BIOS reference guide, before the DDC functions "
		"are dispatched.  This allows the video BIOS DDC functions to "
		"be taken over.  When disabled, 5F45h will not be called."

	Combo	$H46_VESA_PM_Hook, "5F46h - Hook Before VESA VBE/PM:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F46h hook, as specified "
		"in the video BIOS reference guide, before the PM functions "
		"are dispatched.  This will allow the PM functions to be "
		"taken over or for custom setup.  When disabled, 5F46h will "
		"not be called."

	Combo	$H47_Notify_Display_Sw, "5F47h - Notify Display Switch Hook:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F47h hook, as specified "
		"in the video BIOS reference guide, after a new display "
		"combination has been set by the video BIOS.  When disabled, "
		"5F47h will not be called."

	Combo	$H48_After_VESA_PM, "5F48h - Hook After VESA VBE/PM Set Power State:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F48h hook, as specified "
		"in the video BIOS reference guide, after the PM functions "
		"have been executed.  This allows and custom setup to be "
		"reset.  When disabled, 5F48h will not be called."
      Combo $H49_Get_BL_Inv_Pol, "5F49h - Hook to get the backlight inverter type and polarity:", &IntXXh_List,
      Help  "When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F49h hook, as specified "
		"in the video BIOS reference guide, to get the backlight inverter type and "
		"polarity information.  When disabled, 5F49h will not be called."

      #ELSE	; $BIOS_Type == MOBILE

	Combo	$H34_Set_LFP_Fitting, "5F34h - Set Panel Fitting Hook:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F34h hook ,as specified "
		"in the video BIOS reference guide, in the middle of video "
		"BIOS POST.  The returned value will override the default BMP "
		"setting.  When disabled, 5F34h will not be called."

	Combo	$H35_Bootup_Display, "5F35h - Boot Up Display Devices Hook:", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F35h hook, as specified "
		"in the video BIOS reference guide, in the middle of video "
		"BIOS POST.  When disabled, 5F35h will not be called.\r\n"
		"\r\n"
		"Note, Enabling this hook and returning a good display"
		"combination will override the 'Boot Display Algorithm' "
		"table."

	Combo	$H36_Boot_TV_Format, "5F36h - Boot TV Format Hook", &IntXXh_List,
	Help	"When this feature is enabled (Use Interrupt 15h), the video "
		"BIOS will call the interrupt 15h, 5F36h hook, as specified "
		"in the video BIOS reference guide, in the middle of video "
		"BIOS POST.  When disabled, 5F36h will not be called."

	Combo	$H40_Set_Panel_Type, "5F40h - Panel Type Hook:", &IntXXh_List,
	Help	"This feature when enabled (Use interrupt 15h) allows the "
		"system BIOS to return the panel type to be used in booting "
		"the system and from then on by both the video BIOS and "
		"driver.  If disabled, the BMPed panel type will be used."

      #ENDIF	; $BIOS_Type == MOBILE

EndPage


;==============================================================================
; Page - Modes Removal Table
;------------------------------------------------------------------------------

Page "Modes Removal Table"

	Table	$Mode_Rem_Table "Modes Removal Table",
      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
		Column "X-Resolution", 2 bytes, DEC
		Column "Y-Resolution", 2 bytes, DEC 
		Column "BPP", 1 byte, DEC 
		Column "Refresh Rate", 2 bytes, EHEX 
		Column "Removal Flags", 1 byte, EHEX 
		Column "Panel Type", 2 bytes, EHEX,
      #ELSE	; $BIOS_Type == MOBILE
		Column "X-Resolution", 2 bytes, DEC
		Column "Y-Resolution", 2 bytes, DEC 
		Column "BPP", 1 byte, DEC 
		Column "Refresh Rate", 2 bytes, EHEX 
		Column "Removal Flags", 1 byte, EHEX, 
      #ENDIF	; $BIOS_Type == MOBILE
	Help	"This feature allows removing support for selected modes "
		"resolutions.\r\n"
		"\r\n"
		"X-Resolution, Y-Resolution, and BPP in Decimal or "
		"Hexadecimal (0FFFFh or 0FFh means disable all).\r\n"
		"\r\n"
		"Refresh Rate bitmap selection (0 = Do not remove, 1 = "
		"Remove):\r\n"
		"\r\n"
		"\tBit           15-9   8   7  6  5  4  3  2  1   0 \r\n"
		"\tRRate(Hz) Reserved 120 100 85 75 72 70 60 56 43i \r\n"
		"\r\n"
		"Removal Flags bitmap selection (0 = Do not remove, 1 = "
		"Remove):\r\n"
		"\r\n"
		"\tBit                    7               6                        5       4       3       2        1        0    \r\n"
		"\tComponent  Reserved  TV Scan Mode    LFP  EFP  TV  CRT  Driver  VBIOS \r\n"
		"\r\n"
		"\tNote: 1) In order to remove mode from both Windows and DOS, "
		"both Bit 1 and Bit 0 must be set to 1.\r\n"
		"\r\n"
		"\t      2) The defaule setting '0' for Bit6 is for removing "
		"Progressive scan mode from TV device, and setting '1' is for "
		"removing Interlaced scan mode from TV device.\r\n"
		"\r\n"
		"(Mobile only) Panel Type bitmap selection (0 = Do not "
		"remove, 1 = Remove if panel is active):/r/n"
		"\r\n"
		"\tBit  15 14 13 12 11 10  9 8 7 6 5 4 3 2 1 0 \r\n"
		"\tType 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n"
		"\r\n"
		"\tNote: Default is to remove a mode resolution from all "
		"panel types."
EndPage


      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
;==============================================================================
; Page - Display Configuration Removal Table
;------------------------------------------------------------------------------

Page "Display Configuration Removal Table"

	Table	$Dev_Removed_Table " Display Device Configuration Removal Table",
		Column "Pipe B" , 1 byte , BIN
		Column "Pipe A" , 1 byte , BIN, 
		
	Help	"This feature allows blocking selected display configurations "
		"by the video BIOS and driver.\r\n"
		"\r\n"
		"Display Devices are specified in the following bit patterns "
		"(pipe A and B use the same bit pattern):\r\n"
		"\r\n"
		"\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
		"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT\r\n"
		"\r\n"
		"Examples:\r\n"
		"\tPipe B      Pipe A\r\n"
		"\t00000000b,  00000011b  ; TV & CRT on Pipe A\r\n"
		"\t00001100b,  00000001b  ; EFP & LFP on Pipe B and CRT on "
		"Pipe A"
EndPage
      #ENDIF	; $BIOS_Type == MOBILE


;==============================================================================
; Page - OEM Customizable Mode 2.0
;------------------------------------------------------------------------------

Page "OEM Customizable Modes 2.0"

	Link	"OEM Mode 1 Configuration", "OEM Mode #1"
	Link	"OEM Mode 2 Configuration", "OEM Mode #2"
	Link	"OEM Mode 3 Configuration", "OEM Mode #3"
      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
	Link	"OEM Mode 4 Configuration", "OEM Mode #4"
	Link	"OEM Mode 5 Configuration", "OEM Mode #5"
	Link	"OEM Mode 6 Configuration", "OEM Mode #6"	
      #ENDIF	; $BIOS_Type == 1

	Page "OEM Mode #1"

		Link	"Close Table" , ".."

		Title	"     8 bpp = VGA mode 60h / VESA mode 160h"
		Title	"    16 bpp = VGA mode 61h / VESA mode 161h"
		Title	"    32 bpp = VGA mode 62h / VESA mode 162h"

		EditNum	$OEM_Mode_Flags1, "Support Flags:", BIN,
		Help	"Support flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tDriver"
			"\tVBIOS"
			"\r\n"
	
		EditNum	$OEM_Display_Flags1, "Display Flags:", BIN,
		Help	"Display Flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tLFP2"
			"\tEFP2"
			"\tTV2"
			"\tCRT2"
			"\tLFP"
			"\tEFP"
			"\tTV"
			"\tCRT"
			"\r\n"

		Title	"Mode Characteristics"
		EditNum	$OEM_Mode_X1, "  X Resolution:", DEC,
		Help	"X Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Y1, "  Y Resolution:", DEC,
		Help	"Y Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Color1, "  Color Depth:", BIN,
		Help	"Color Depth, bits can be set simultaneously (binary)."
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\t32 BPP"
			"\t16 BPP"
			"\t8 BPP"
			"\r\n"

		EditNum	$OEM_Mode_RRate1, "  Refresh Rate:", DEC,
		Help	"Refresh rate for OEM customizable mode (decimal)."
		Link "18 Bytes DTD" , "DTD"

		Page "DTD"

			Link	"Close Table" , ".."

			Table	$OEM_Mode_DTD1 " Detailed Timings Descriptor",
				Column "Timings" , 1 byte , EHEX,
			Help	"This table is the 18-byte DTD(Detailed Timings"
				" Descriptor) structure defined in the VESA"
				" EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage
	EndPage
	
	Page "OEM Mode #2"

		Link	"Close Table" , ".."

		Title	"     8 bpp = VGA mode 63h / VESA mode 163h"
		Title	"    16 bpp = VGA mode 64h / VESA mode 164h"
		Title	"    32 bpp = VGA mode 65h / VESA mode 165h"

			EditNum	$OEM_Mode_Flags2, "Support Flags:", BIN,
		Help	"Support flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tDriver"
			"\tVBIOS"
			"\r\n"
		
		EditNum	$OEM_Display_Flags2, "Display Flags:", BIN,
		Help	"Display Flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tLFP2"
			"\tEFP2"
			"\tTV2"
			"\tCRT2"
			"\tLFP"
			"\tEFP"
			"\tTV"
			"\tCRT"
			"\r\n"

		Title	"Mode Characteristics"

		EditNum	$OEM_Mode_X2, "  X Resolution:", DEC,
		Help	"X Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Y2, "  Y Resolution:", DEC,
		Help	"Y Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Color2, "  Color Depth:", BIN,
		Help	"Color Depth, bits can be set simultaneously (binary)."
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\t32 BPP"
			"\t16 BPP"
			"\t8 BPP"
			"\r\n"

		EditNum	$OEM_Mode_RRate2, "  Refresh Rate:", DEC,
		Help	"Refresh rate for OEM customizable mode (decimal)."

		Link "18 Bytes DTD" , "DTD"

		Page "DTD"

			Link	"Close Table" , ".."

			Table	$OEM_Mode_DTD2 " Detailed Timings Descriptor",
				Column "Timings" , 1 byte , EHEX,
			Help	"This table is the 18-byte DTD(Detailed Timings"
				" Descriptor) structure defined in the VESA"
				" EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage
	EndPage

	Page "OEM Mode #3"

		Link	"Close Table" , ".."

		Title	"     8 bpp = VGA mode 66h / VESA mode 166h"
		Title	"    16 bpp = VGA mode 67h / VESA mode 167h"
		Title	"    32 bpp = VGA mode 68h / VESA mode 168h"

		EditNum	$OEM_Mode_Flags3, "Support Flags:", BIN,
		Help	"Support flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tDriver"
			"\tVBIOS"
			"\r\n"
		
		EditNum	$OEM_Display_Flags3, "Display Flags:", BIN,
		Help	"Display Flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tLFP2"
			"\tEFP2"
			"\tTV2"
			"\tCRT2"
			"\tLFP"
			"\tEFP"
			"\tTV"
			"\tCRT"
			"\r\n"

		Title	"Mode Characteristics"

		EditNum	$OEM_Mode_X3, "  X Resolution:", DEC,
		Help	"X Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Y3, "  Y Resolution:", DEC,
		Help	"Y Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Color3, "  Color Depth:", BIN,
		Help	"Color Depth, bits can be set simultaneously (binary)."
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\t32 BPP"
			"\t16 BPP"
			"\t8 BPP"
			"\r\n"

		EditNum	$OEM_Mode_RRate3, "  Refresh Rate:", DEC,
		Help	"Refresh rate for OEM customizable mode (decimal)."

		Link "18 Bytes DTD" , "DTD"

		Page "DTD"

			Link	"Close Table" , ".."

			Table	$OEM_Mode_DTD3 " Detailed Timings Descriptor",
				Column "Timings" , 1 byte , EHEX,
			Help	"This table is the 18-byte DTD(Detailed Timings"
				" Descriptor) structure defined in the VESA"
				" EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage
	EndPage

      #IF	$BIOS_Type == 1		; $BIOS_Type == MOBILE
	Page "OEM Mode #4"

		Link	"Close Table" , ".."

		Title	"     8 bpp = VGA mode 69h / VESA mode 169h"
		Title	"    16 bpp = VGA mode 6Ah / VESA mode 16Ah"
		Title	"    32 bpp = VGA mode 6Bh / VESA mode 16Bh"

		EditNum	$OEM_Mode_Flags4, "Support Flags:", BIN,
		Help	"Support flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tDriver"
			"\tVBIOS"
			"\r\n"
	
		EditNum	$OEM_Display_Flags4, "Display Flags:", BIN,
		Help	"Display Flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tLFP2"
			"\tEFP2"
			"\tTV2"
			"\tCRT2"
			"\tLFP"
			"\tEFP"
			"\tTV"
			"\tCRT"
			"\r\n"

		Title	"Mode Characteristics"

		EditNum	$OEM_Mode_X4, "  X Resolution:", DEC,
		Help	"X Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Y4, "  Y Resolution:", DEC,
		Help	"Y Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Color4, "  Color Depth:", BIN,
		Help	"Color Depth, bits can be set simultaneously (binary)."
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\t32 BPP"
			"\t16 BPP"
			"\t8 BPP"
			"\r\n"

		EditNum	$OEM_Mode_RRate4, "  Refresh Rate:", DEC,
		Help	"Refresh rate for OEM customizable mode (decimal)."

		Link "18 Bytes DTD" , "DTD"

		Page "DTD"

			Link	"Close Table" , ".."

			Table	$OEM_Mode_DTD4 " Detailed Timings Descriptor",
				Column "Timings" , 1 byte , EHEX,
			Help	"This table is the 18-byte DTD(Detailed Timings"
				" Descriptor) structure defined in the VESA"
				" EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage
	EndPage

	Page "OEM Mode #5"

		Link	"Close Table" , ".."

		Title	"     8 bpp = VGA mode 6Ch / VESA mode 16Ch"
		Title	"    16 bpp = VGA mode 6Dh / VESA mode 16Dh"
		Title	"    32 bpp = VGA mode 6Eh / VESA mode 16Eh"

		EditNum	$OEM_Mode_Flags5, "Support Flags:", BIN,
		Help	"Support flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tDriver"
			"\tVBIOS"
			"\r\n"
	
		EditNum	$OEM_Display_Flags5, "Display Flags:", BIN,
		Help	"Display Flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tLFP2"
			"\tEFP2"
			"\tTV2"
			"\tCRT2"
			"\tLFP"
			"\tEFP"
			"\tTV"
			"\tCRT"
			"\r\n"

		Title	"Mode Characteristics"

		EditNum	$OEM_Mode_X5, "  X Resolution:", DEC,
		Help	"X Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Y5, "  Y Resolution:", DEC,
		Help	"Y Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Color5, "  Color Depth:", BIN,
		Help	"Color Depth, bits can be set simultaneously (binary)."
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\t32 BPP"
			"\t16 BPP"
			"\t8 BPP"
			"\r\n"

		EditNum	$OEM_Mode_RRate5, "  Refresh Rate:", DEC,
		Help	"Refresh rate for OEM customizable mode (decimal)."

		Link "18 Bytes DTD" , "DTD"

		Page "DTD"

			Link	"Close Table" , ".."

			Table	$OEM_Mode_DTD5 " Detailed Timings Descriptor",
				Column "Timings" , 1 byte , EHEX,
			Help	"This table is the 18-byte DTD(Detailed Timings"
				" Descriptor) structure defined in the VESA"
				" EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage
	EndPage

	Page "OEM Mode #6"

		Link	"Close Table" , ".."

		Title	"     8 bpp = VGA mode 6Fh / VESA mode 16Fh"
		Title	"    16 bpp = VGA mode 70h / VESA mode 170h"
		Title	"    32 bpp = VGA mode 71h / VESA mode 171h"

		EditNum	$OEM_Mode_Flags6, "Support Flags:", BIN,
		Help	"Support flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tDriver"
			"\tVBIOS"
			"\r\n"
		
		EditNum	$OEM_Display_Flags6, "Display Flags:", BIN,
		Help	"Display Flags:"
			"(0 = Disabled, 1 = Enabled)"
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tLFP2"
			"\tEFP2"
			"\tTV2"
			"\tCRT2"
			"\tLFP"
			"\tEFP"
			"\tTV"
			"\tCRT"
			"\r\n"

		Title	"Mode Characteristics"

		EditNum	$OEM_Mode_X6, "  X Resolution:", DEC,
		Help	"X Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Y6, "  Y Resolution:", DEC,
		Help	"Y Resolution in pixels (decimal)."

		EditNum	$OEM_Mode_Color6, "  Color Depth:", BIN,
		Help	"Color Depth, bits can be set simultaneously (binary)."
			"\r\n\r\n"
			"\tBit 7"
			"\tBit 6"
			"\tBit 5"
			"\tBit 4"
			"\tBit 3"
			"\tBit 2"
			"\tBit 1"
			"\tBit 0"
			"\r\n"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\tRsvd"
			"\t32 BPP"
			"\t16 BPP"
			"\t8 BPP"
			"\r\n"

		EditNum	$OEM_Mode_RRate6, "  Refresh Rate:", DEC,
		Help	"Refresh rate for OEM customizable mode (decimal)."

		Link "18 Bytes DTD" , "DTD"

		Page "DTD"

			Link	"Close Table" , ".."

			Table	$OEM_Mode_DTD6 " Detailed Timings Descriptor",
				Column "Timings" , 1 byte , EHEX,
			Help	"This table is the 18-byte DTD(Detailed Timings"
				" Descriptor) structure defined in the VESA"
				" EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage
	EndPage
      #ENDIF	; $BIOS_Type == 1
EndPage


      #IF	$Integrated_EFP == 1	; $Integrated_EFP == TRUE
;==============================================================================
; Page - Integrated HDMI/DisplayPort Configuration
;------------------------------------------------------------------------------

Page "Integrated HDMI/DisplayPort Configuration with External Connectors"
	Title	"Configurations for HDMI/DisplayPort Solution (External Connectors):"

	Link "Device 1 Configuration" , "Device 1"
	Link "Device 2 Configuration" , "Device 2"

	Page "Device 1"

		Link	"Close Window" , ".."

		Combo	$Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
		Help	"This feature specifies the Device Type for this "
			"add-in device."

		Combo	$Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List,
		Help	"This feature specifies which DVO port the device is "

		Combo	$Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"This feature specifies the GPIO pin pair "
			"used as DDC bus by this device.  If this device "
			"doesn't support DDC bus, this field will be ignored."

		Combo	$Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
		Help	"This feature specifies the AUX Channel for int-DisplayPort. "
			"This field is valid only if integrated DP is selected for Device Type."

;		Combo	$Int_EFP1_Docked_Port, "Select Port for Dock/Undock Support:", &Int_EFP_Port_List,
;		Help	"This feature selects the port that can be use "
;			"for docking station support \r\n"
;			"\r\n"
;			"This is the driver-only feature."
			
;		Combo	$Int_EFP1_HDMI_Compat, "HDMI Compatibility Support:", &No_Yes_List,
;		Help	"This feature will be valid only when DisplayPort is selected "
;			"as the Device Type.  Select 'Yes' to this feature will allow "
;			"for HDMI enabled via DisplayPort\r\n"
;			"\r\n"
;			"This is the driver-only feature."

;		Combo	$Int_EFP1_Conn_Info, "Connector Type:", &Int_EFP_Connector_Info,
;		Help	"This feature will allow users to select connector type "
;			"for this device\r\n"
;			"\r\n"
;			"This is the driver-only feature."
	EndPage

	Page "Device 2"

		Link	"Close Window" , ".."

		Combo	$Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
		Help	"This feature specifies the Device Type for this "
			"add-in device."

		Combo	$Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List,
		Help	"This feature specifies which DVO port the device is "

		Combo	$Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"This feature specifies the GPIO pin pair "
			"used as DDC bus by this device.  If this device "
			"doesn't support DDC bus, this field will be ignored."

		Combo	$Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
		Help	"This feature specifies the AUX Channel for int-DisplayPort. "
			"This field is valid only if integrated DP is selected for Device Type."

;		Combo	$Int_EFP2_Docked_Port, "Select Port for Dock/Undock Support:", &Int_EFP_Port_List,
;		Help	"This feature selects the port that can be use "
;			"for docking station support \r\n"
;			"\r\n"
;			"This is the driver-only feature."
			
;		Combo	$Int_EFP2_HDMI_Compat, "HDMI Compatibility Support:", &No_Yes_List,
;		Help	"This feature will be valid only when DisplayPort is selected "
;			"as the Device Type.  Select 'Yes' to this feature will allow "
;			"for HDMI enabled via DisplayPort\r\n"
;			"\r\n"
;			"This is the driver-only feature."

;		Combo	$Int_EFP2_Conn_Info, "Connector Type:", &Int_EFP_Connector_Info,
;		Help	"This feature will allow users to select connector type "
;			"for this device\r\n"
;			"\r\n"
;			"This is the driver-only feature."

	EndPage

EndPage
      #ENDIF	; $Integrated_EFP == 1	; $Integrated_EFP == TRUE

#IF	$Chipset != 2
;==============================================================================
; Page - Add-In Devices data structures
;------------------------------------------------------------------------------

Page "Motherboard-Down SDVO Devices"
	Title	"SDVO Device Configurations for Motherboard-Down Solution:"

	Link "Device 1 Configuration" , "Device 1"
	Link "Device 2 Configuration" , "Device 2"

	Page "Device 1"

		Link	"Close Window" , ".."

		Combo	$Dev1_Type, "Select Device Type:", &Device_Type_List,
		Help	"This feature specifies the Device Type for this "
			"add-in device."

		Combo	$Dev1_DVO, "Select DVO Port:", &DVO_Port_List,
		Help	"This feature specifies which DVO port the device is "
			"attached."

		Combo	$Dev1_I2C_Pin, "Select I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"This feature specifies the GPIO pin pair used as I2C "
			"bus by the attached device in order to read and "
			"write to the device registers."

		EditNum	$Dev1_Slave_Add, "Enter I2C Device Address:", EHEX,
		Help	"This feature specifies the I2C device address for "
			"this device for reading and writing device "
			"registers.  The device address should be in 8-bit "
			"format with the 7-bit slave address assigned to its "
			"bits 7:1 and bit 0 set to 0.\r\n"
			"Note: For Integrated HDMI use address 00h"

		Combo	$Dev1_I2CSpeed, "Select Max I2C codec speed:", &GMBus_Speed_List,
		Help	"This feature selects the max I2C bus speed supported by the device. "
			"This speed will be used to communicate with the device"

		Combo	$Dev1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"This feature selects specifies the GPIO pin pair "
			"used as DDC bus by this device.  If this device "
			"doesn't support DDC bus, this field will be ignored."

	EndPage

	Page "Device 2"

		Link	"Close Window" , ".."

		Combo	$Dev2_Type, "Select Device Type:", &Device_Type_List,
		Help	"This feature specifies the Device Type for this "
			"add-in device."

		Combo	$Dev2_DVO, "Select DVO Port:", &DVO_Port_List,
		Help	"This feature specifies which DVO port the device is "
			"attached."

		Combo	$Dev2_I2C_Pin, "Select I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"This feature specifies the GPIO pin pair used as I2C "
			"bus by the attached device in order to read and "
			"write to the device registers."

		EditNum	$Dev2_Slave_Add, "Enter I2C Device Address:", EHEX,
		Help	"This feature specifies the I2C device address for "
			"this device for reading and writing device "
			"registers.  The device address should be in 8-bit "
			"format with the 7-bit slave address assigned to its "
			"bits 7:1 and bit 0 set to 0.\r\n"
			"Note: For Integrated HDMI use address 00h"

		Combo	$Dev2_I2CSpeed, "Select Max I2C codec speed:", &GMBus_Speed_List,
		Help	"This feature selects the max I2C bus speed supported by the device. "
			"This speed will be used to communicate with the device"

		Combo	$Dev2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"This feature selects specifies the GPIO pin pair "
			"used as DDC bus by this device.  If this device "
			"doesn't support DDC bus, this field will be ignored."

	EndPage

EndPage

#ENDIF	; Not supported in Pineview

;==============================================================================
; Page - Dot Clock Override Table
;------------------------------------------------------------------------------

Page "Dot Clock Override Table"

	Table	$Clock_Override_Table "Dot Clock Override Values",
		Column "Frequency (KHz)", 4 bytes, DEC
		Column "N", 1 byte, EHEX 
		Column "M1", 1 byte, EHEX 
		Column "M2", 1 byte, EHEX 
		Column "P1 Post Divisor", 1 byte, EHEX 
		Column "P2 Clock Divide", 1 byte, EHEX, 
	Help	"The dot clock override table will allow for the modification "
		"of up to 10 specific dot clock values to generate the "
		"specific timings for the "
		"specified dot clock.\r\n"
		"\r\n"
		"Frequency = The dot clock value to modify (e.g. 25000KHz to "
		"modify dot clock for 640x480@60Hz)\r\n"
		"\r\n"
		"PLL Register's\r\n"
		"N  = 1 Byte value in Hex\r\n"
		"M1 = 1 Byte value in Hex\r\n"
		"M2 = 1 Byte value in Hex\r\n"
		"P1 Post Divisor = 1 Byte value in Hex\r\n"
		"P2 Clock Divide = 1 Byte value in Hex"

EndPage

;============================================================================
; Page - LVDS Configuration
;----------------------------------------------------------------------------

Page	"LFP Configuration"
	Link	"Close Table", ".."
	Combo	$LVDS_Config , "Active Local Flat Panel Configuration", &LVDS_Config_List,
	Help	"This feature is for configuring LFP usage. "
EndPage

      #IF	$LVDS_Config == 2 ; SDVO LVDS 
;============================================================================
; Page - SDVO LVDS Page
;----------------------------------------------------------------------------

Page "LFP (SDVO LVDS) Features"

	Link "General SDVO LVDS Features" , "General SDVO-LVDS Features"
	Link "Panel #1", "Panel #1"
	Link "Panel #2", "Panel #2"
	Link "Panel #3", "Panel #3"
	Link "Panel #4", "Panel #4"


	Page	"General SDVO-LVDS Features"
		Link	"Close Table" , ".."

	Combo	$LVDS_H40_Set_Panel_Type , "5F40h - Panel Type Hook", &Disabled_Enabled_List,
	Help	"This feature when enabled (Use interrupt 15h) allows the "
		"system BIOS to return the panel type to be used in booting "
		"the system and from then on by both the video BIOS and "
		"driver.  If disabled, the BMPed panel type will be used."

	Combo	$LVDS_Panel_Type , "Select Panel Type:", &SDVO_Panel_List,
	Help	"This feature selects the Local Flat Panel (LFP) the VBIOS "
		"and driver is to enable.\r\n" 
		"\r\n"
		"Note, a valid return from the system BIOS hook 5F40h will "
		"replace this default value.\r\n"
		"\r\n"
		"Default LFP parameter values:\r\n"
		"\tPANEL #01: 1024x768 LVDS\r\n"
		"\tPANEL #02: 1280x1024 LVDS\r\n"
		"\tPANEL #03: 1400x1050 LVDS\r\n"
		"\tPANEL #04: 1600x1200 LVDS\r\n "

	EditNum	$LVDS_Init_Backlight, "Panel Backlight Value:", DEC,
	Help	"This feature is for initializing the panel's backlight. "

	EditNum	$LVDS_SSC_CLK_FREQ, "LVDS Spread Spectrum Clock Frequency:", DEC,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"

	Title	"Ambient Light Trip Values:"
	EditNum	$LVDS_ALS_Low_Trip, "     ALS Low Trip:", DEC,
	Help	"This feature is for initializing the ambient light sensor's low trip value. "

	EditNum	$LVDS_ALS_High_Trip, "     ALS High Trip:", DEC,
	Help	"This feature is for initializing the ambient light sensor's high trip value. "

	Combo	$LVDS_Panel_Fitting , "Panel Scaling:", &Disabled_Enabled_List,
	Help	"This feature can be used for enabling or disabling scaling. "

	Title	"Up Scalar Coefficients:"
	EditNum	$Scalar_Coef_0, "     Coefficient 0", EHEX,
	Help	"Scalar Coefficient 0. "
	EditNum	$Scalar_Coef_1, "     Coefficient 1", EHEX,
	Help	"Scalar Coefficient 1. "
	EditNum	$Scalar_Coef_2, "     Coefficient 2", EHEX,
	Help	"Scalar Coefficient 2. "
	EditNum	$Scalar_Coef_3, "     Coefficient 3", EHEX,
	Help	"Scalar Coefficient 3. "
	EditNum	$Scalar_Coef_4, "     Coefficient 4", EHEX,
	Help	"Scalar Coefficient 4. "
	EditNum	$Scalar_Coef_5, "     Coefficient 5", EHEX,
	Help	"Scalar Coefficient 5. "
	EditNum	$Scalar_Coef_6, "     Coefficient 6", EHEX,
	Help	"Scalar Coefficient 6. "
	EditNum	$Scalar_Coef_7, "     Coefficient 7", EHEX,
	Help	"Scalar Coefficient 7. "


	Combo	$LVDS_Dither, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable Dithering. "

	Combo	$LVDS_Panel_Connector, "Panel Connector:", &Panel_Connector_List,
	Help	"This feature will select the type of panel connector. "

	Combo	$LVDS_SSC, "LVDS SSC Support:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LVDS "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LVDS PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SSC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LVDS Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."

	Combo	$LVDS_SSC_DualTwin_Disb, "Disable Dual Twin if LVDS SSC Enabled:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."

	Title	"Panel Protection Setting:"
	Combo	$LVDS_Monitor_Hsync, "     Monitor HSync:", &Off_On_List,
	Help	"This feature will enable or disable monitoring of HSync for panel protection. "

	Combo	$LVDS_Monitor_Vsync, "     Monitor VSync:", &Off_On_List,
	Help	"This feature will enable or disable monitoring of VSync for panel protection. "

	Combo	$LVDS_Monitor_Pixel, "     Monitor Pixel:", &Off_On_List,
	Help	"This feature will enable or disable monitoring of the pixel clock for panel protection. "
	
	EndPage


	Page	"Panel #1"

		Combo	$LVDS_Panel_1_Channel_Type, "LVDS Channel:", &LVDS_Channel_List,
		Help	"This feature will allow you to choose the channel type for the LVDS panel\r\n "
			"NOTE: The channel type is dependant upon what the panel supports. "

		Combo	$LVDS_Panel_1_Color_Depth, "Panel Color Depth:", &Panel_Color_Depth_List,
		Help	"This feature specifies the color depth of the SDVO LVDS panel used. "

		Link "Panel #1 DTD", "Panel #1 DTD"
		Link "Panel #1 PnPID", "Panel #1 PnPID"
		Link "Panel #1 Power Sequencing", "Panel #1 Power Sequencing"
		Link	"Close Table", ".."

	   	Page	"Panel #1 DTD"
			Link	"Close Table", ".."

			Table	$LFP_DTD_01 " DTD for Panel #1",
				Column "DTD", 1 byte, EHEX,
			Help	"This feature allows for the definition of the DVO "
				"port timings parameters related to the LFP.  The "
				"table is the 18-byte DTD structure defined in the "
				"VESA EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage

	   	Page	"Panel #1 PnPID"
			Link	"Close Table", ".."
			Table	$LFP_PID_01 " PnP ID for Panel #1",
				Column "PnP ID", 1 byte, EHEX,
			Help	"This feature allows the 10 bytes of EDID Vendor / "
				"Product ID starting at offset 08h to be used as a "
				"PnP ID.\r\n"
				"\r\n"
				" Table Definition:\r\n"
				"  Word:  ID Manufacturer Name\r\n"
				"  Word:  ID Product Code\r\n"
				"  DWord: ID Serial Number\r\n"
				"  Byte:  Week of Manufacture\r\n"
				"  Byte:  Year of Manufacture"
		EndPage

	   	Page	"Panel #1 Power Sequencing"
			Link	"Close Table", ".."

		Table	$LFP_Pwr_Seq_01 " Power Sequencing for Panel #1",
				Column "T0 - T4", 2 byte, DEC,
			Help	"This feature specifies the panel power sequencing times. \r\n"
				"T0 is the time in the power on sequence from PANEL POWER ON to LVDS SIGNALS ON. \r\n"
				"T1 is the time in the power on sequence from LVDS SIGNALS ON to BACKLIGHT ON. \r\n"
				"T2 is the time in the power off sequence from BACKLIGHT OFF to LVDS SIGNALS OFF. \r\n"
				"T3 is the time in the power off sequence from LVDS SIGNALS OFF to PANEL POWER OFF. \r\n"
				"T4 is the panel’s power up delay time.  T4 is the minimum time from PANEL POWER OFF to PANEL POWER ON. \r\n"
		EndPage
	EndPage

	Page	"Panel #2"

		Combo	$LVDS_Panel_2_Channel_Type, "LVDS Channel:", &LVDS_Channel_List,
		Help	"This feature will allow you to choose the channel type for the LVDS panel\r\n "
			"NOTE: The channel type is dependant upon what the panel supports. "

		Combo	$LVDS_Panel_2_Color_Depth, "Panel Color Depth:", &Panel_Color_Depth_List,
		Help	"This feature specifies the color depth of the SDVO LVDS panel used. "

		Link "Panel #2 DTD", "Panel #2 DTD"
		Link "Panel #2 PnPID", "Panel #2 PnPID"
		Link "Panel #2 Power Sequencing", "Panel #2 Power Sequencing"
		Link	"Close Table", ".."

	   	Page	"Panel #2 DTD"
			Link	"Close Table", ".."

			Table	$LFP_DTD_02 " DTD for Panel #2",
				Column "DTD", 1 byte, EHEX,
			Help	"This feature allows for the definition of the DVO "
				"port timings parameters related to the LFP.  The "
				"table is the 18-byte DTD structure defined in the "
				"VESA EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage

	   	Page	"Panel #2 PnPID"
			Link	"Close Table", ".."
			Table	$LFP_PID_02 " PnP ID for Panel #2",
				Column "PnP ID", 1 byte, EHEX,
			Help	"This feature allows the 10 bytes of EDID Vendor / "
				"Product ID starting at offset 08h to be used as a "
				"PnP ID.\r\n"
				"\r\n"
				" Table Definition:\r\n"
				"  Word:  ID Manufacturer Name\r\n"
				"  Word:  ID Product Code\r\n"
				"  DWord: ID Serial Number\r\n"
				"  Byte:  Week of Manufacture\r\n"
				"  Byte:  Year of Manufacture"
		EndPage

	   	Page	"Panel #2 Power Sequencing"
			Link	"Close Table", ".."

			Table	$LFP_Pwr_Seq_02 " Power Sequencing for Panel #2",
				Column "T0 - T4", 2 byte, DEC,
			Help	"This feature specifies the panel power sequencing times. \r\n"
				"T0 is the time in the power on sequence from PANEL POWER ON to LVDS SIGNALS ON. \r\n"
				"T1 is the time in the power on sequence from LVDS SIGNALS ON to BACKLIGHT ON. \r\n"
				"T2 is the time in the power off sequence from BACKLIGHT OFF to LVDS SIGNALS OFF. \r\n"
				"T3 is the time in the power off sequence from LVDS SIGNALS OFF to PANEL POWER OFF. \r\n"
				"T4 is the panel’s power up delay time.  T4 is the minimum time from PANEL POWER OFF to PANEL POWER ON. \r\n"
		EndPage
	EndPage

	Page	"Panel #3"

		Combo	$LVDS_Panel_3_Channel_Type, "LVDS Channel:", &LVDS_Channel_List,
		Help	"This feature will allow you to choose the channel type for the LVDS panel\r\n "
			"NOTE: The channel type is dependant upon what the panel supports. "

		Combo	$LVDS_Panel_3_Color_Depth, "Panel Color Depth:", &Panel_Color_Depth_List,
		Help	"This feature specifies the color depth of the SDVO LVDS panel used. "

		Link "Panel #3 DTD", "Panel #3 DTD"
		Link "Panel #3 PnPID", "Panel #3 PnPID"
		Link "Panel #3 Power Sequencing", "Panel #3 Power Sequencing"
		Link	"Close Table", ".."

	   	Page	"Panel #3 DTD"
			Link	"Close Table", ".."

			Table	$LFP_DTD_03 " DTD for Panel #3",
				Column "DTD", 1 byte, EHEX,
			Help	"This feature allows for the definition of the DVO "
				"port timings parameters related to the LFP.  The "
				"table is the 18-byte DTD structure defined in the "
				"VESA EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage

	   	Page	"Panel #3 PnPID"
			Link	"Close Table", ".."
			Table	$LFP_PID_03 " PnP ID for Panel #3",
				Column "PnP ID", 1 byte, EHEX,
			Help	"This feature allows the 10 bytes of EDID Vendor / "
				"Product ID starting at offset 08h to be used as a "
				"PnP ID.\r\n"
				"\r\n"
				" Table Definition:\r\n"
				"  Word:  ID Manufacturer Name\r\n"
				"  Word:  ID Product Code\r\n"
				"  DWord: ID Serial Number\r\n"
				"  Byte:  Week of Manufacture\r\n"
				"  Byte:  Year of Manufacture"
		EndPage

	   	Page	"Panel #3 Power Sequencing"
			Link	"Close Table", ".."

			Table	$LFP_Pwr_Seq_03 " Power Sequencing for Panel #3",
				Column "T0 - T4", 2 byte, DEC,
			Help	"This feature specifies the panel power sequencing times. \r\n"
				"T0 is the time in the power on sequence from PANEL POWER ON to LVDS SIGNALS ON. \r\n"
				"T1 is the time in the power on sequence from LVDS SIGNALS ON to BACKLIGHT ON. \r\n"
				"T2 is the time in the power off sequence from BACKLIGHT OFF to LVDS SIGNALS OFF. \r\n"
				"T3 is the time in the power off sequence from LVDS SIGNALS OFF to PANEL POWER OFF. \r\n"
				"T4 is the panel’s power up delay time.  T4 is the minimum time from PANEL POWER OFF to PANEL POWER ON. \r\n"
		EndPage
	EndPage

	Page	"Panel #4"

		Combo	$LVDS_Panel_4_Channel_Type, "LVDS Channel:", &LVDS_Channel_List,
		Help	"This feature will allow you to choose the channel type for the LVDS panel\r\n "
			"NOTE: The channel type is dependant upon what the panel supports. "

		Combo	$LVDS_Panel_4_Color_Depth, "Panel Color Depth:", &Panel_Color_Depth_List,
		Help	"This feature specifies the color depth of the SDVO LVDS panel used. "

		Link "Panel #4 DTD", "Panel #4 DTD"
		Link "Panel #4 PnPID", "Panel #4 PnPID"
		Link "Panel #4 Power Sequencing", "Panel #4 Power Sequencing"
		Link	"Close Table", ".."

	   	Page	"Panel #4 DTD"
			Link	"Close Table", ".."

			Table	$LFP_DTD_04 " DTD for Panel #4",
				Column "DTD", 1 byte, EHEX,
			Help	"This feature allows for the definition of the DVO "
				"port timings parameters related to the LFP.  The "
				"table is the 18-byte DTD structure defined in the "
				"VESA EDID version 1.x.\r\n"  
				"\r\n"
				"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
				"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
				"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
				"\tDB ?\t; Vertical Active in lines, LSB\r\n"
				"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
				"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
				"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
				"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
				"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
				"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
				"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
				"\tDB ?\t; Horizontal Image Size, LSB\r\n"
				"\tDB ?\t; Vertical Image Size, LSB\r\n"
				"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
				"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
				"\tDB 0\t; Horizontal Border in pixels\r\n"
				"\tDB 0\t; Vertical Border in lines\r\n"
				"\tDB ?\t; Flags:\r\n"
				"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
				"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
				"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
				"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
				"\t    \t;   Bit 0:   0 = Reserved"
		EndPage

	   	Page	"Panel #4 PnPID"
			Link	"Close Table", ".."
			Table	$LFP_PID_04 " PnP ID for Panel #4",
				Column "PnP ID", 1 byte, EHEX,
			Help	"This feature allows the 10 bytes of EDID Vendor / "
				"Product ID starting at offset 08h to be used as a "
				"PnP ID.\r\n"
				"\r\n"
				" Table Definition:\r\n"
				"  Word:  ID Manufacturer Name\r\n"
				"  Word:  ID Product Code\r\n"
				"  DWord: ID Serial Number\r\n"
				"  Byte:  Week of Manufacture\r\n"
				"  Byte:  Year of Manufacture"
		EndPage

	   	Page	"Panel #4 Power Sequencing"
			Link	"Close Table", ".."

			Table	$LFP_Pwr_Seq_04 " Power Sequencing for Panel #4",
				Column "T0 - T4", 2 byte, DEC,
			Help	"This feature specifies the panel power sequencing times. \r\n"
				"T0 is the time in the power on sequence from PANEL POWER ON to LVDS SIGNALS ON. \r\n"
				"T1 is the time in the power on sequence from LVDS SIGNALS ON to BACKLIGHT ON. \r\n"
				"T2 is the time in the power off sequence from BACKLIGHT OFF to LVDS SIGNALS OFF. \r\n"
				"T3 is the time in the power off sequence from LVDS SIGNALS OFF to PANEL POWER OFF. \r\n"
				"T4 is the panel’s power up delay time.  T4 is the minimum time from PANEL POWER OFF to PANEL POWER ON. \r\n"
		EndPage
	EndPage
	
EndPage
      #ENDIF	; $LVDS_Config == 2 ; SDVO LVDS

      #IF	($LVDS_Config == 1) || ($LVDS_Config == 3) ; Int LVDS or eDP
;============================================================================
; Page - Integrated LVDS Page
;----------------------------------------------------------------------------
      #IF	$LVDS_Config == 1 ; Int LVDS
Page "LFP (Integrated LVDS) Features"
      #ELSEIF	$LVDS_Config == 3 ; Int LVDS
Page "LFP (eDP) Features"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 ; Int LVDS
	Link "LVDS Dot Clock Override Table" , "LVDS Dot Clock Override Table"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS
	Link "LFP Display Configuration" , "LFP Display Configuration"
	Link "Panel #1 ", "Panel #1 "
	Link "Panel #2 ", "Panel #2 "
	Link "Panel #3 ", "Panel #3 "
	Link "Panel #4 ", "Panel #4 "
	Link "Panel #5 ", "Panel #5 "
	Link "Panel #6 ", "Panel #6 "
	Link "Panel #7 ", "Panel #7 "
	Link "Panel #8 ", "Panel #8 "
	Link "Panel #9 ", "Panel #9 "
	Link "Panel #10 ", "Panel #10 "
	Link "Panel #11 ", "Panel #11 "
	Link "Panel #12 ", "Panel #12 "
	Link "Panel #13 ", "Panel #13 "
	Link "Panel #14 ", "Panel #14 "
	Link "Panel #15 ", "Panel #15 "
	Link "Panel #16 ", "Panel #16 "

;==============================================================================
; Page - LVDS Dot Clock Override Table
;------------------------------------------------------------------------------

      #IF	$LVDS_Config == 1 ; Int LVDS
Page "LVDS Dot Clock Override Table"

	Table	$LVDS_Clock_Override_Tbl "LVDS Dot Clock Override Values",
		Column "Frequency (KHz)", 4 bytes, DEC
		Column "N", 1 byte, EHEX 
		Column "M1", 1 byte, EHEX 
		Column "M2", 1 byte, EHEX 
		Column "P1 Post Divisor", 1 byte, EHEX
		Column "P2 Clock Divide", 1 byte, EHEX, 
	Help	"The dot clock override table will allow for the modification "
		"of up to 10 specific dot clock values to generate the "
		"specific timings for the "
		"specified dot clock.\r\n"
		"\r\n"
		"Frequency = The dot clock value to modify (e.g. 25000KHz to "
		"modify dot clock for 640x480@60Hz)\r\n"
		"\r\n"
		"PLL Register's\r\n"
		"N  = 1 Byte value in Hex\r\n"
		"M1 = 1 Byte value in Hex\r\n"
		"M2 = 1 Byte value in Hex\r\n"
		"P1 Post Divisor = 1 Byte value in Hex\r\n"
		"P2 Clock Divide = 1 Byte value in Hex"

EndPage
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

;==============================================================================
; Page - LVDS Features
;------------------------------------------------------------------------------

Page "LFP Display Configuration"

	Combo	$bmp_Panel_type, "Select Panel Type:", &Panel_List, 
	Help	"This feature selects the Local Flat Panel (LFP) the VBIOS "
		"and driver is to enable.\r\n" 
		"\r\n"
		"For Pineview Do NOT Select panel resolutions greater then "
		"1280x1024 as it is not supported.\r\n" 
		"\r\n"
		"Note, a valid return from the system BIOS hook 5F40h will "
		"replace this default value.\r\n"
		"\r\n"
		"Default LFP parameter values:\r\n"
		"\tPANEL #01: 640x480 LVDS\r\n"
		"\tPANEL #02: 800x600 LVDS\r\n"
		"\tPANEL #03: 1024x768 LVDS\r\n"
		"\tPANEL #04: 1280x1024 LVDS\r\n "
		"\tPANEL #05: 1400x1050 Reduced Blanking LVDS\r\n"
		"\tPANEL #06: 1400x1050 Non-Reduced Blanking LVDS\r\n"
		"\tPANEL #07: 1600x1200 LVDS\r\n"
		"\tPANEL #08: 1280x768 LVDS\r\n"
		"\tPANEL #09: 1680x1050 LVDS\r\n"
		"\tPANEL #10: 1920x1200 LVDS\r\n"
		"\tPANEL #11: Reserved\r\n"
		"\tPANEL #12: Reserved\r\n "
		"\tPANEL #13: Reserved\r\n"
		"\tPANEL #14: 1280x800 LVDS\r\n"
		"\tPANEL #15: 1280x600 LVDS\r\n"
      #IF	$Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; CAL, CRL, PSB		
		"\tPANEL #16: 2048x1536 LVDS"
      #ELSE
		"\tPANEL #16: Reserved"      
      #ENDIF	; $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; CAL, CRL, PSB

	Combo	$bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List,
	Help	"This feature, when enabled, will activate support for a LFP "
		"with an EDID.  The video BIOS and drivers will load the EDID "
		"and use its data to set appropriate timing on current panel.  "
		"If disabled, there will be no attempt to read an EDID and other methods "
		"will be used to set panel timing."
		"\r\n\r\nNote:  The backlight data may need to be updated." 
		"\r\n       The <LFP DDC GPIO pin pair> option on page General"
		" Features must be correct for platform."

EndPage

;==============================================================================
; Page - Panel #1 (640x480 LVDS) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #1 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_01, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_01, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

       #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards	
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
       #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
       #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_1_Channel_Type, "Integrated LVDS Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LVDS Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LVDS Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LVDS Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
		"			   X > 1280, Set LVDS for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LVDS for Single Channel.\r\n"
		"			   Y => 1024, Set LVDS for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth01, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LVDS panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither01, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC01, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq01, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT01, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC01, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq01, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP
      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_01, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
		"rate will not adversely impact the user experience\r\n"
		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
		"based on the power state and on updates to the display\r\n"
		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
      
       #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards	
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
	
		EditNum	$Power_On_Backlight_Enable_Delay_01, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_01, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_01, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_01, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_01, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
			
	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_01 " Power Sequencing for Panel #1",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13

	Page "LFP Parameters"
	
		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_01 " LFP Registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB

	EndPage
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"
	
		Link	"Close Table" , ".."

		Table	$DVO_Tbl_01 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_01 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_1, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_1, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_1, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_1, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_1, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_1, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_1, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_1, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_01, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_01, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_01, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_01, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP

EndPage

;==============================================================================
; Page - Panel #2 (800x600 LVDS) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #2 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_02, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_02, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

       #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards	
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
       #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
       #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_2_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth02, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither02, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC02, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq02, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT02, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC02, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq02, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_02, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
		"which reduces display power\r\n"
		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
		"rate will not adversely impact the user experience\r\n"
		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
		"based on the power state and on updates to the display\r\n"
		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
      #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards	
      #IF	$LVDS_Config == 1 ; iLVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
	
		EditNum	$Power_On_Backlight_Enable_Delay_02, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_02, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_02, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_02, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_02, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
			

	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_02 " Power Sequencing for Panel #2",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13 
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_02 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage

      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_02 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_02 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_2, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_2, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_2, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_2, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_2, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_2, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_2, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_2, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_02, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_02, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_02, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_02, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #3 (1024x768 LVDS) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #3 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_03, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_03, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_3_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth03, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither03, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC03, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq03, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT03, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC03, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq03, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_03, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_03, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_03, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_03, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_03, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_03, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
			

	EndPage
      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_03 " Power Sequencing for Panel #3",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS

      #ELSE	; $chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_03 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
     #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage
     #ENDIF	; $chipset >= 13

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_03 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_03 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_3, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_3, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_3, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_3, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_3, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_3, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_3, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_3, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_03, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_03, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_03, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_03, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #4 (1280x1024 LVDS) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #4 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_04, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_04, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13 
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_4_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth04, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither04, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC04, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq04, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT04, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC04, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq04, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_04, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_04, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_04, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_04, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_04, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_04, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"

	EndPage
      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_04 " Power Sequencing for Panel #4",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_04 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_04 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_04 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_4, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_4, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_4, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_4, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_4, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_4, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_4, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_4, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_04, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_04, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_04, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_04, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #5 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #5 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_05, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_05, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_5_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth05, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither05, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC05, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq05, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT05, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC05, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq05, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_05, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_05, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_05, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_05, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_05, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_05, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"

	EndPage
      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_05 " Power Sequencing for Panel #5",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_05 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage
      #ENDIF	; $Chipset >= 13
	

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_05 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_05 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_5, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_5, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_5, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_5, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_5, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_5, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_5, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_5, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_05, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_05, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_05, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_05, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #6 (1400x1050) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #6 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_06, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_06, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
      #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_6_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth06, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither06, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC06, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq06, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT06, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC06, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq06, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_06, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
      #IF	$Chipset >= 13; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_06, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_06, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_06, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_06, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_06, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_06 " Power Sequencing for Panel #6",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_06 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_06 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_06 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_6, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_6, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_6, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_6, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_6, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_6, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_6, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_6, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_06, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_06, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_06, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_06, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #7 (1600x1200) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #7 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_07, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_07, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_7_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth07, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither07, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC07, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq07, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT07, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC07, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq07, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_07, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_07, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_07, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_07, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_07, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_07, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"

	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_07 " Power Sequencing for Panel #7",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_07 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB

	EndPage
      #ENDIF	; $Chipset >= 13
      
	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_07 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_07 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_7, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_7, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_7, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_7, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_7, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_7, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_7, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_5, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_07, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_07, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_07, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_07, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #8 (1280x768) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #8 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_08, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_08, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
      #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_8_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth08, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither08, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC08, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq08, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT08, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC08, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq08, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_08, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_08, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_08, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_08, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_08, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_08, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_08 " Power Sequencing for Panel #8",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_08 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB

	EndPage
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_08 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_08 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_8, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_8, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_8, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_8, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_8, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_8, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_8, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_8, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_08, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_08, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_08, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_08, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #9 (1680x1050) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #9 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_09, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_09, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_9_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth09, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither09, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC09, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq09, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT09, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC09, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq09, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_09, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"

		Link	"Close Table" , ".."

		EditNum	$Power_On_Backlight_Enable_Delay_09, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_09, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_09, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_09, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_09, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage
      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_09 " Power Sequencing for Panel #9",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_09 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB

	EndPage
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"


		Link	"Close Table" , ".."

		Table	$DVO_Tbl_09 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_09 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_9, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_9, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_9, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_9, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_9, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_9, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_9, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_9, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_09, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_09, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_09, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_09, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP

	
EndPage

;==============================================================================
; Page - Panel #10 (1920x1200) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #10 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_10, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_10, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_10_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth10, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither10, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC10, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq10, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT10, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC10, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq10, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_10, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_10, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_10, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_10, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_10, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_10, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_10 " Power Sequencing for Panel #10",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_10 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_10 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_10 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_10, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_10, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_10, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_10, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_10, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_10, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_10, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_10, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_10, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_10, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_10, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_10, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #11 (Reserved) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #11 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_11, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_11, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_11_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth11, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither11, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; && $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC11, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq11, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT11, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC11, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq11, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_11, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_11, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_11, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_11, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_11, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_11, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_11 " Power Sequencing for Panel #11",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_11 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB

	EndPage
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_11 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_11 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_11, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_11, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_11, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_11, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_11, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_11, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_11, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_11, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_11, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_11, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_11, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_11, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #12 (Reserved) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #12 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_12, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_12, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
      #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_12_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth12, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither12, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC12, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq12, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT12, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC12, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq12, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_12, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."

		EditNum	$Power_On_Backlight_Enable_Delay_12, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_12, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_12, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_12, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_12, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_12 " Power Sequencing for Panel #12",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_12 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage

      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"


		Link	"Close Table" , ".."

		Table	$DVO_Tbl_12 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_12 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_12, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_12, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_12, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_12, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_12, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_12, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_12, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_12, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_12, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_12, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_12, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_12, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #13 (Reserved) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #13 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_13, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_13, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_13_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth13, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither13, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC13, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq13, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT13, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC13, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq13, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_13, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_13, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_13, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_13, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_13, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_13, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_13 " Power Sequencing for Panel #13",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage

     #ENDIF	; $LVDS_Config == 1 ; Int LVDS
     #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_13 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage
	
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"


		Link	"Close Table" , ".."

		Table	$DVO_Tbl_13 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_13 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_13, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_13, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_13, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_13, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_13, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_13, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_13, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_13, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_13, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_13, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_13, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_13, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #14 (1280x800) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #14 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_14, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_14, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 11 ; $Chipset == ALVISO || $Chipset == CAL || $Chipset == PSB
			"\r\nNote:  The sequencing delay values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 11 ; $Chipset == ALVISO || $Chipset == CAL || $Chipset == PSB

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_14_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth14, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither14, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC14, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq14, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT14, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC14, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq14, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_14, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"

		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_14, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_14, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_14, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_14, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_14, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage

      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_14 " Power Sequencing for Panel #14",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_14 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage

      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"


		Link	"Close Table" , ".."

		Table	$DVO_Tbl_14 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_14 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_14, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_14, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_14, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_14, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_14, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_14, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_14, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_14, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_14, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_14, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_14, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_14, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #15 (1280x600) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #15 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_15, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_15, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_15_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth15, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither15, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC15, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq15, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT15, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC15, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq15, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_15, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"

		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_15, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_15, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_15, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_15, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_15, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage
      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_15 " Power Sequencing for Panel #15",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13

	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_15 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB

	EndPage
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_15 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_15 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_15, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_15, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_15, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_15, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_15, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_15, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_15, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_15, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_15, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_15, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_15, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_15, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage

;==============================================================================
; Page - Panel #16 (Reserved) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #16 "

	Title	"Local Flat Panel (LFP) Size"

	EditNum	$Panel_Width_16, "LFP Width:", DEC,
	Help	"This value specifies the LFP pixel width for this panel "
		"type."

	EditNum	$Panel_Height_16, "LFP Height:", DEC,
	Help	"This value specifies the LFP pixel height (number of scan "
		"lines) for this panel type."

     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
	Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      #ELSE
	Link "LFP Parameter Table" , "LFP Parameters"
     #ENDIF	; $Chipset >= 13
	Link "DTD Timings Table" , "DTD Timings"
	Link "LFP PnP ID Table" , "LFP PnP ID"
	Link "Backlight Control Parameters" , "Backlight Control Parameters"

      #IF	$LVDS_Config == 1 && $Chipset != 2 ; Int LVDS
	Combo	$Int_LVDS_Panel_16_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
	Help	"SETTINGS :\r\n"
		"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
		"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
		"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control in respect to Channel Selection.\r\n"
		"Compare X-Resolution to 1280: X < 1280, Set LFP for Single Channel.\r\n"
		"			   X > 1280, Set LFP for Dual Channel.\r\n"
		"			   X = 1280, Check Y-Resolution.\r\n"
		"Compare Y-Resolution to 1024: Y < 1024, Set LFP for Single Channel.\r\n"
		"			   Y => 1024, Set LFP for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 1 && $Chipset >= 10; int LVDS and >= CRL
	Combo	$INT_Panel_Color_Depth16, "Panel Color Depth:", &Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 && $Chipset >= 10

      #IF	$LVDS_Config == 3 ; eDP
	Combo	$eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
	Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP
		
      #IF	$Chipset >= 13; CTG onwards
	Combo	$Enable_Dither16, "Dithering:", &Off_On_List,
	Help	"This feature will enable or disable dithering. "
      #ENDIF	; $Chipset >= 13

      #IF	$LVDS_Config == 1 ; Int LVDS
	Title	"Spread Spectrum Clock Features"
	Combo	$Enable_SSC16, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature when enabled will instruct software to use the "
		"external Spread Spectrum input clock as the internal LFP "
		"PLL reference clock.  Otherwise, when disabled, the internal "
		"reference clock will be used as the internal LFP PLL "
		"reference clock ignoring any Spread Spectrum input clock.\r\n"
		"\r\n"
		"Note: When enabling SCC option, please make sure that the hardware/"
		"system BIOS has enabled this feature in the chipset platform. "
		"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
		"option must match the actual SCC frequency determined by platform "
		"hardware and/or system BIOS."
		"\r\n"
		"Note: This option is for internal LFP only.\r\n"
		"\r\n"
		"Note: Currently, this feature will also replace the CRT PLL "
		"reference clock on the same pipe that may cause CRT jitter.  "
		"Ideas to help this situation are to remove single pipe "
		"simultaneous display combinations (dual display twin) or use "
		"the 'Disable SSC in Dual Display Twin' option to "
		"automatically switch back to internal reference clock when "
		"entering a dual display twin display combination."
	Combo	$SSC_Freq16, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
	Combo	$Disable_SSC_DDT16, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
	Help	"This feature allows a selectable option for OEMs to disable "
		"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
		"Pipe Simultaneous mode.\r\n"
		"\r\n"
		"Note: Disabling means that SSC will not be enabled while "
		"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
		"when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
	Title	"eDP Spread Spectrum Clock Features"
	Combo	$Enable_SSC16, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
	Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
	Combo	$SSC_Freq16, "  eDP Spread Spectrum Clock Frequency:", &SSC_List,
	Help	"The SSC frequency selected must match the actual SCC frequency "
		"determined by platform hardware and/or system BIOS.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS

      #IF	$LVDS_Config == 3 ; eDP
	Link "eDP Link Parameters" , "eDP Link Parameters"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	$Chipset == 13; CTG
       Title	"DPS Panel Type Features"
       Combo	$DPS_Panel_Type_16, "  DPS Panel Type:", &DPS_Panel_Type_List,
       Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
       		"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
       		"which reduces display power\r\n"
       		"SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience\r\n"
       		"D2P0:-  Dynamically switches the LCD panel refresh rate in progressive scan mode\r\n"
       		"based on the power state and on updates to the display\r\n"
       		"Seamless:-  Allows power savings when on battery mode and when a lower refresh\r\n"
       		"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
       		"rate switching, which eliminates the screen blink that occurred\r\n" 
		"during the refresh rate transitions\r\n"
      #ENDIF    ; $Chipset
     #IF	$Chipset >= 13 || $Chipset == 2 ; CTG onwards
      #IF	$LVDS_Config == 1 ; Int LVDS
	Page "Panel Power Sequencing"
	
		Link	"Close Table" , ".."
		
		EditNum	$Power_On_Backlight_Enable_Delay_16, "  Power On to Backlight Enable Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for delay of power on to backlight enable."


		EditNum	$PowerUpDelay_16, "  Panel Power Up Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for panel power up delay. Note: This value "
			"is typically T1 + T2."

		EditNum	$Power_Backlight_Off_Power_Down_Delay_16, "  Power Backlight Off to Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power backlight off to power down delay."

		EditNum	$PowerDownDelay_16, "  Panel Power Down Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power down delay."
			
		EditNum	$PowerCycleDelay_16, "  Panel Power Cycle Delay Time:", DEC,
		Help	"This feature specifies the panel power sequencing time "
			"for power Cycle delay."
			"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programming value should be 5 instead of 4"
	EndPage
      #ELSEIF	$LVDS_Config == 3 ; eDP
   	Page	"Panel Power Sequencing"
		Link	"Close Table", ".."

		Table	$eDP_Pwr_Seq_16 " Power Sequencing for Panel #16",
			Column "VESA eDP Tx Values", 2 byte, DEC,
		Help	"This feature specifies the panel power sequencing times.  "
			"The delay time unit is in 100us.\r\n"
			"\r\n"
			"T1 + T2 (Row 1) -  Power-Up delay. \r\n"
			"T5 (Row 2) - Power-On to Backlight Enable delay. \r\n"
			"T6 (Row 3) - Backlight-Off to Power-Down delay. \r\n"
			"T3 (Row 4) - Power-Down delay. \r\n"
			"T4 (Row 5) - Power cycle delay. \r\n"
	EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS
      #ELSE	; $Chipset >= 13
	Page "LFP Parameters"

		Link	"Close Table" , ".."

		Table	$LVDS_Tbl_16 " LFP registers",
			Column "Address" , 4 bytes , EHEX
			Column "Data" , 4 bytes , EHEX, 
		Help	"This table allows for the modification of control "
			"parameters related to the Local Flat Panel (LFP).\r\n"
			"\r\n"
			"  00061180h - Port Control\r\n"
			"  00061208h - Panel Power On Sequencing\r\n"
			"  0006120Ch - Panel Power Off Sequencing\r\n"
			"  00061210h - Panel Power Cycle Delay and Reference\r\n"
			"  00061230h - Panel Fitting Control"
      #IF	$Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
			"\r\nNote:  The Panel Power Cycle Dealy and Reference values to be programmed with '+1'. For instance, "
			"to have a delay of 400ms, programing value should be 5 instead of 4"
      #ENDIF	; $Chipset == 5 || $Chipset == 8 || $Chipset == 10 || $Chipset == 11 ; ALVISO, CAL, CRL, PSB
	EndPage
      #ENDIF	; $Chipset >= 13

	Page "DTD Timings"

		Link	"Close Table" , ".."

		Table	$DVO_Tbl_16 " DTD Timings Values",
			Column "Timings" , 1 byte , EHEX,
		Help	"This feature allows for the definition of the DTD "
			"port timings parameters related to the LFP.  The "
			"table is the 18-byte DTD structure defined in the "
			"VESA EDID version 1.x.\r\n"  
			"\r\n"
			"\tDB ?\t; Low Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; High Byte of DClk in 10 KHz\r\n"
			"\tDB ?\t; Horizontal Active in pixels, LSB\r\n"
			"\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
			"\tDB ?\t; Vertical Active in lines, LSB\r\n"
			"\tDB ?\t; Vertical Blanking in lines, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
			"\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n"
			"\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
			"\t    \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
			"\t    \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
			"\t    \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
			"\t    \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
			"\tDB ?\t; Horizontal Image Size, LSB\r\n"
			"\tDB ?\t; Vertical Image Size, LSB\r\n"
			"\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
			"\t    \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
			"\tDB 0\t; Horizontal Border in pixels\r\n"
			"\tDB 0\t; Vertical Border in lines\r\n"
			"\tDB ?\t; Flags:\r\n"
			"\t    \t;   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
			"\t    \t;   Bit 6-5: 00 = Reserved\r\n"
			"\t    \t;   Bit 4-3: 11 = Digital Separate\r\n"
			"\t    \t;   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
			"\t    \t;   Bit 0:   0 = Reserved"

	EndPage

	Page "LFP PnP ID"

		Link	"Close Table" , ".."

		Table	$LVDS_PnP_ID_16 " LFP PnP ID Values",
			Column "PnP ID" , 1 byte , EHEX,
		Help	"This feature allows the 10 bytes of EDID Vendor / "
			"Product ID starting at offset 08h to be used as a "
			"PnP ID.\r\n"
			"\r\n"
			" Table Definition:\r\n"
			"  Word:  ID Manufacturer Name\r\n"
			"  Word:  ID Product Code\r\n"
			"  DWord: ID Serial Number\r\n"
			"  Byte:  Week of Manufacture\r\n"
			"  Byte:  Year of Manufacture"

	EndPage

	Page "Backlight Control Parameters"

		Link	"Close Table" , ".."

		Combo	$BLC_Inv_Type_16, "  Inverter Type:", &Inv_Type_List,
		Help	"This feature allows for the selection of the "
			"Backlight Inverter type that is to be used to "
			"control the backlight brightness of the LFP.  When "
			"PWM is selected, the driver and VBIOS will control "
			"the backlight brightness via the integrated PWM "
			"solution for the applicable chipsets.  When I2C is "
			"selected, the driver and VBIOS will control the "
			"backlight brightness via the I2C solution for the "
			"applicable chipsets.  When None/External is "
			"selected, the system BIOS will control the backlight "
			"brightness via the external solution."

		Combo	$BLC_Inv_Polarity_16, "  Inverter Polarity:", &Inv_Polarity_List,
		Help	"This feature allows the backlight inverter polarity "
			"to be specified.\r\n"
			"\r\n"
			"Normal means 0 value is minimum brightness.\r\n"
			"Inverted means 0 value is maximum brightness."

		EditNum	$BLC_Min_Brightness_16, "  Minimum Brightness:", DEC,
		Help	"This feature allows defining the absolute minimum "
			"backlight brightness setting.  The graphics driver "
			"will never decrease the backlight less than this "
			"value.  The value must be specified using normal "
			"polarity semantics."

		EditNum	$PWM_Frequency_16, "  PWM Inverter Frequency (Hz):", DEC,
		Help	"This feature allows for the definition of the "
			"frequency needed for PWM Inverter.\r\n"
			"\r\n"
			"Note: The frequency range, entered as a decimal "
			"number, for the integrated PWM is 200Hz - 40KHz."

		Combo	$BLC_GPIO_Pins_16, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
		Help	"Selects the GPIO pin pair to use as the I2C bus for "
			"this device."

		Combo	$BLC_GMBus_Speed_16, "  I2C Bus Frequency:", &GMBus_Speed_List,
		Help	"Selects the I2C bus frequency to use when "
			"communicating to this device."

		EditNum	$BLC_I2C_Addr_16, "  I2C Device Address:", HEX,
		Help	"Selects the I2C device address for communication to "
			"this backlight inverter.  The device address should "
			"be in 8-bit format with the slave address assigned to "
			"bits 7:1 and bit 0 cleared.  For example, the slave "
			"address 0101100b would be stated here as 58h."

		EditNum	$BLC_Brightness_Cmd_16, "  I2C Device, Display Brightness Command Code:", HEX,
		Help	"Selects the command code (register index) for setting "
			"the backlight brightness."
	EndPage

      #IF	$LVDS_Config == 3 ; eDP
	Page "eDP Link Parameters"

		Link	"Close Table" , ".."
		
		Combo	$eDP_Link_DataRate_16, "  Data Rate:", &eDP_Link_DataRate_List,
		Help	"This feature allows for the selection of the "
			"Data Rate for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_LaneCount_16, "  Lane Count:", &eDP_Link_LaneCount_List,
		Help	"This feature allows for the selection of the "
			"Lane Count (Port Width) for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

		Combo	$eDP_Link_PreEmp_16, "  Pre-Emphasis:", &eDP_Link_PreEmp_List,
		Help	"This feature allows for the selection of the "
			"Pre-emphasis value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."
			
		Combo	$eDP_Link_Vswing_16, "  Voltage Swing:", &eDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
			"Voltage Swing value for the embedded DP link. It will be used if the "
			"sink indicates that no aux handshake is required during link training."

	EndPage

      #ENDIF	; $LVDS_Config == 3 ; eDP
	
EndPage	; "Panel #16 "

EndPage ; "Integrated LFP Features"
      #ENDIF	; ($LVDS_Config == 1) || ($LVDS_Config == 3) ; Int LVDS or eDP


;==============================================================================
; Page - Test Page 1 (General)
;------------------------------------------------------------------------------

Page "Test Page 1 (General)"

;	Title	"|------------- Maximum Length of revision note. --------------------|"

	Title	" Note:  This page is for test purposes only.  Default values should "
	Title	"        not be changed for released software."

     #IF	$Chipset == 5	; $Chipset == ALV
	Combo	$Flexaim_Support, "  MBI Downloading Support: ", &Disabled_Enabled_List,
	Help	"Enable MBI interface to download Flexaim and VBT dynamically "
		"from system BIOS. "

	Combo	$Download_Ext_VBT, "  Download External VBT: ", &No_Yes_List,
	Help	"Whether the external VBT should be downloaded from "
		"System BIOS and overrides the VBIOS VBT and AIM VBT's. "
     #ENDIF	; $Chipset == 5	; $Chipset == ALV

     #IF 	$BIOS_Type == 0 	; $BIOS_Type == DESKTOP
	Combo	$SV_Dis_Arbiter, "  Disable VGA Fast Arbiter: ", &No_Yes_List,
	Help	"If select Yes, the VGA Fast Arbiter is Disabled for the following "
			"combinations: \r\n"
			"1) FSB533/DDR266 \r\n"
			"2) FSB400/DDR266 \r\n"
			"3) FSB533/DDR200 \r\n"
			"\r\n"
			"If selec No, the VGA Fast Arbiter is always enabled"

	Combo	$SV_Setmode_No_DVO, "  Setmode without Update DVO timings: ", &No_Yes_List,
	Help	"If select Yes, VBIOS setmode will skip DVO update.\r\n"
			"If select No, VBIOS setmode will update DVO timings"
     #ENDIF	; $BIOS_Type == DESKTOP
	Combo	$SV_Wait_Timeout_Hang, "  Allow Wait VBlank Timeout Hang: ", &No_Yes_List,
	Help	"If select Yes, VBIOS will allow software hang when Wait VBlank is timed out."

	Combo	$RelStage, "  VBIOS Release Stage:", &RelStage,
	Help	"This is the stage of the video BIOS Release.   Selecting "
		"'Evaluation' will cause an evaluation message to be "
		"displayed with the signon messages.\r\n"
		"\r\n"
		"Evaluation allows AIM modules to be included for testing, "
		"but forces a 10 second POST delay to assure it is not "
		"shipped in evaluation mode.\r\n"
		"\r\n"
		"Production means OEMs can use it for production and there "
		"won't be a forced evaluation message or delay of 10 second "
		"during boot."

EndPage


;============================================================================
; Page - Test Page 2 (Register Tables)
;----------------------------------------------------------------------------

Page "Test Page 2 (Register Tables)"

;	Title	"|------------- Maximum Length of revision note. --------------------|"

	Title	" Note:  This page (including to following table pages) are for test "
	Title	"        purposes only.  Default values should not be changed for "
	Title	"        released software."

	Link "MMIO Register Boot Table" , "MMIO Boot Registers"
	Link "I/O SW Flag Register Table" , "I/O SW Flag Registers"
	Link "MMIO SW Flag Register Table" , "MMIO SW Flag Registers"

	Page "MMIO Boot Registers"

		Link	"Close Table" , ".."

		Table	$MMIO_Boot_Table "MMIO Registers",
		Column "Address", 4 bytes, EHEX
		Column "Data", 4 bytes, EHEX, 
		Help	"This is a memory mapped I/O register boot table.  "
			"This table is loaded during video BIOS POST.  The "
			"data as well as the address are double words." 

	EndPage

	Page "I/O SW Flag Registers"

		Link	"Close Table" , ".."

		Table	$SWF_IO_Table "I/O Software flag Registers",
			Column "Address", 1 bytes, EHEX
			Column "Data", 1 bytes, EHEX, 
		Help	"This is a I/O software flag boot table.  This "
			"table is loaded during video BIOS POST.  The data "
			"as well as the address are bytes." 

	EndPage

	Page "MMIO SW Flag Registers"

		Link	"Close Table" , ".."

		Table	$SWF_MMIO_Table "MMIO Software flag Registers",
			Column "Address", 4 bytes, EHEX
			Column "Data", 4 bytes, EHEX, 
		Help	"This is a MMIO software flag boot table.  This "
			"table is loaded during video BIOS POST.  The data "
			"as well as the address are DWORDs." 

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