This file lists the ported tools of ALLIANCE 3.0 with a short discription.
		(text is extracted from alliance man-pages)

ALLIGATOR 	(LCA2VBE) is a FPGA optimizer tool that allows mapping from
		behavioral VHDL into commercial programmable architectures
		such as Xilinx.

AMG 		is an modified booth algorithm array multiplier generator.

ASIMUT 		is a native VHDL logic simulator.

BBR 		is a pitchless channel router for two preplaced blocks.

BSG 		is a barrel shifter generator.

DESB 		is a functional abstractor disassembler for CMOS circuits.
		It provides a data-flow VHDL description from a transistor
		netlist of a circuit.

DLX_ASM 	is a assembler for the DLX processor.

DPR 		is a specialized placement and routing tool for bitsliced
		datapaths.

DREAL		is a hierarchical real layout editor,
		requires XFree86/LessTif.

DRUC		is a general parametrized VLSI design rule checker.

FPGEN
		(FPGEN-105, GENERICGNG, ADD2SG, AND2G, AND3G, BUFFG, BUSEG,
		CONSTG, INVG, MUX2CSG, MUX3CDG, MUX3CSG, MUX4CSG, MUX5CSG,
		MUX6CSG, NAND2G, NAND2MASKG, NAND3G, NBUSEG, NMUX2CSG, NOR2G,
		NOR2MASKG, NOR3G, NPL1G, NULG, OR2G, OR3G, PDFFG, PDFFNWG,
		PDFFNWQG, PDFFQG, PDFFRG, PDFFRTG, PDFFTG, PDFFTQG, PL1G,
		PMSG, PMSNWG, PMSNWQG, PMSQG, PMSTG, PMSTQG, XNOR2G,
		XNOR2MASKG, XOR2G)
		is a set of C functions dedicated to data-path synthesis.

GENLIB		is a procedural language for netlist capture and placement
		description.

GENPAT		is a language interpreter dedicated to efficient simulation
		patterns descriptions to be taken as input of asimut.

GENVIEW		(GENVIEW_C11 GENVIEW_GCC WATCHDOG) is a genlib plus C
		graphical source-level debugger under XFree86.

GRAAL		is a hierarchical symbolic layout editor,
		requires XFree86/LessTif.

GROG		is a generic ROM generator. 

L2P, LAYOUT2PAPER
		creates a PostScript file from a symbolic layout file, or
		from a physical layout file.

LOGIC		is a logic synthesis tool. The input is data-flow VHDL,
		the output is a netlist of gates.

LVX		is a gate level net compare tool.

LYNX		(FLATRDS) is a layout extractor. The output is an extracted
		netlist with parasitic capacitances.

NETOPTIM	permits to remove fanout problems within a gates netlist
		and to optimize the delay.

PROOF 		performs a formal comparison between two data-flow VHDL
		descriptions.

RAGE		is a RAM generator.

RFG		is a static register file generator.

RING		is a core to pad router.

RSA		is a fast adder/substractor generator.

S2R		performs the translation from the symbolic to physical
		layout for the foundry.

SCR		is a place and route tool for standard cells.

SYF		is a Finite State Machine synthesizer.

TAS		is a switch level, pattern independant, timing analyzer for
		CMOS circuits.

*******	Last tools, usage makes little sense without CHEOPS:

FRIN, FROUT, ALC2KH, KH2ALC, X2Y
		These tools convert Cheops files from and to Alliance
		descriptions. (Cheops available only for SUN-Systems)
