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PIC16F527
CONFIG (address:0x0FFF, mask:0x03FF)
FOSC -- Oscillator Selection
| FOSC = LP | 0x0FF8 | LP oscillator and automatic 18 ms DRT (DRTEN ignored). |
| FOSC = XT | 0x0FF9 | XT oscillator and automatic 18 ms DRT (DRTEN ignored). |
| FOSC = HS | 0x0FFA | HS oscillator and automatic 18 ms DRT (DRTEN ignored). |
| FOSC = EC | 0x0FFB | EC oscillator with I/O function on OSC2/CLKOUT and 10 us startup time. |
| FOSC = INTRC_IO | 0x0FFC | INTRC with I/O function on OSC2/CLKOUT and 10 us startup time. |
| FOSC = INTRC_CLKOUT | 0x0FFD | INTRC with CLKOUT function on OSC2/CLKOUT and 10 us startup time. |
| FOSC = EXTRC_IO | 0x0FFE | EXTRC with I/O function on OSC2/CLKOUT and 10 us startup time. |
| FOSC = EXTRC_CLKOUT | 0x0FFF | EXTRC with CLKOUT function on OSC2/CLKOUT and 10 us startup time. |
WDTE -- Watchdog Timer Enable
| WDTE = OFF | 0x0FF7 | WDT Disabled. |
| WDTE = ON | 0x0FFF | WDT Enabled. |
CP -- Code Protection - User Program Memory
| CP = ON | 0x0FEF | Code protection on. |
| CP = OFF | 0x0FFF | Code protection off. |
MCLRE -- Master Clear Enable
| MCLRE = OFF | 0x0FDF | MCLR pin functions as I/O, MCLR internally tied to Vdd. |
| MCLRE = ON | 0x0FFF | MCLR pin functions as MCLR. |
IOSCFS -- Internal Oscillator Frequency Select
| IOSCFS = 4MHz | 0x0FBF | 4 MHz INTOSC Speed. |
| IOSCFS = 8MHz | 0x0FFF | 8 MHz INTOSC Speed. |
CPSW -- Code Protection - Self Writable Memory
| CPSW = ON | 0x0F7F | Code protection on. |
| CPSW = OFF | 0x0FFF | Code protection off. |
BOREN -- Brown-out Reset Enable
| BOREN = OFF | 0x0EFF | BOR Disabled. |
| BOREN = ON | 0x0FFF | BOR Enabled. |
DRTEN -- Device Reset Timer Enable
| DRTEN = OFF | 0x0DFF | DRT Disabled. |
| DRTEN = ON | 0x0FFF | DRT Enabled (18 ms). |

This page generated automatically by the device-help.pl program (2013-08-01 15:50:26 UTC) from the 8bit_device.info file (rev: 1.14) of mpasmx and from the gputils source package (rev: svn 983:985). The mpasmx is included in the MPLAB X.