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- Features
- Configuration Bits
- RAM map
- SFR map

PIC18F4431
CONFIG1H (address:0x300001, mask:0xCF)
OSC -- Oscillator Selection bits
| OSC = LP | 0xF0 | LP oscillator. |
| OSC = XT | 0xF1 | XT oscillator. |
| OSC = HS | 0xF2 | HS oscillator. |
| OSC = RC2 | 0xF3 | External RC oscillator, CLKO function on RA6. |
| OSC = EC | 0xF4 | EC oscillator, CLKO function on RA6. |
| OSC = ECIO | 0xF5 | EC oscillator, port function on RA6. |
| OSC = HSPLL | 0xF6 | HS oscillator, PLL enabled (clock frequency = 4 x FOSC1). |
| OSC = RCIO | 0xF7 | External RC oscillator, port function on RA6. |
| OSC = IRCIO | 0xF8 | Internal oscillator block, port function on RA6 and port function on RA7. |
| OSC = IRC | 0xF9 | Internal oscillator block, CLKO function on RA6 and port function on RA7. |
| OSC = RC1 | 0xFA | 101X External RC oscillator, CLKO function on RA6. |
| OSC = RC | 0xFC | 11XX External RC oscillator, CLKO function on RA6. |
FCMEN -- Fail-Safe Clock Monitor Enable bit
| FCMEN = OFF | 0xBF | Fail-Safe Clock Monitor disabled. |
| FCMEN = ON | 0xFF | Fail-Safe Clock Monitor enabled. |
IESO -- Internal External Oscillator Switchover bit
| IESO = OFF | 0x7F | Internal External Switchover mode disabled. |
| IESO = ON | 0xFF | Internal External Switchover mode enabled. |
CONFIG2L (address:0x300002, mask:0x0F)
PWRTEN -- Power-up Timer Enable bit
| PWRTEN = ON | 0xFE | PWRT enabled. |
| PWRTEN = OFF | 0xFF | PWRT disabled. |
BOREN -- Brown-out Reset Enable bits
| BOREN = OFF | 0xFD | Brown-out Reset disabled. |
| BOREN = ON | 0xFF | Brown-out Reset enabled. |
BORV -- Brown Out Reset Voltage bits
| BORV = 45 | 0xF3 | VBOR set to 4.5V. |
| BORV = 42 | 0xF7 | VBOR set to 4.2V. |
| BORV = 27 | 0xFB | VBOR set to 2.7V. |
| BORV = 20 | 0xFF | Reserved. |
CONFIG2H (address:0x300003, mask:0x3F)
WDTEN -- Watchdog Timer Enable bit
| WDTEN = OFF | 0xFE | WDT disabled (control is placed on the SWDTEN bit). |
| WDTEN = ON | 0xFF | WDT enabled. |
WDPS -- Watchdog Timer Postscale Select bits
| WDPS = 1 | 0xE1 | 1:1. |
| WDPS = 2 | 0xE3 | 1:2. |
| WDPS = 4 | 0xE5 | 1:4. |
| WDPS = 8 | 0xE7 | 1:8. |
| WDPS = 16 | 0xE9 | 1:16. |
| WDPS = 32 | 0xEB | 1:32. |
| WDPS = 64 | 0xED | 1:64. |
| WDPS = 128 | 0xEF | 1:128. |
| WDPS = 256 | 0xF1 | 1:256. |
| WDPS = 512 | 0xF3 | 1:512. |
| WDPS = 1024 | 0xF5 | 1:1024. |
| WDPS = 2048 | 0xF7 | 1:2048. |
| WDPS = 4096 | 0xF9 | 1:4096. |
| WDPS = 8192 | 0xFB | 1:8192. |
| WDPS = 16384 | 0xFD | 1:16384. |
| WDPS = 32768 | 0xFF | 1:32768. |
WINEN -- Watchdog Timer Window Enable bit
| WINEN = ON | 0xDF | WDT window enabledbled. |
| WINEN = OFF | 0xFF | WDT window disabled. |
CONFIG3L (address:0x300004, mask:0x3C)
PWMPIN -- PWM output pins Reset state control
| PWMPIN = ON | 0xFB | PWM outputs drive active states upon Reset. |
| PWMPIN = OFF | 0xFF | PWM outputs disabled upon Reset (default). |
LPOL -- Low-Side Transistors Polarity
| LPOL = LOW | 0xF7 | PWM0, 2, 4 and 6 are active-low. |
| LPOL = HIGH | 0xFF | PWM0, 2, 4 and 6 are active-high. |
HPOL -- High-Side Transistors Polarity
| HPOL = LOW | 0xEF | PWM1, 3, 5 and 7 are active-low. |
| HPOL = HIGH | 0xFF | PWM1, 3, 5 and 7 are active-high. |
T1OSCMX -- Timer1 Oscillator MUX
| T1OSCMX = OFF | 0xDF | Standard (legacy) Timer1 oscillator operation. |
| T1OSCMX = ON | 0xFF | Low-power Timer1 operation when microcontroller is in Sleep mode. |
CONFIG3H (address:0x300005, mask:0x9D)
FLTAMX -- FLTA MUX bit
| FLTAMX = RD4 | 0xFE | FLTA input is multiplexed with RD4. |
| FLTAMX = RC1 | 0xFF | FLTA input is multiplexed with RC1. |
SSPMX -- SSP I/O MUX bit
| SSPMX = RD1 | 0xFB | SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2, respectively. SDO output is multiplexed with RD1. |
| SSPMX = RC7 | 0xFF | SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output is multiplexed with RC7. |
PWM4MX -- PWM4 MUX bit
| PWM4MX = RD5 | 0xF7 | PWM4 output is multiplexed with RD5. |
| PWM4MX = RB5 | 0xFF | PWM4 output is multiplexed with RB5. |
EXCLKMX -- TMR0/T5CKI External clock MUX bit
| EXCLKMX = RD0 | 0xEF | TMR0/T5CKI external clock input is multiplexed with RD0. |
| EXCLKMX = RC3 | 0xFF | TMR0/T5CKI external clock input is multiplexed with RC3. |
MCLRE -- MCLR Pin Enable bit
| MCLRE = OFF | 0x7F | Disabled. |
| MCLRE = ON | 0xFF | Enabled. |
CONFIG4L (address:0x300006, mask:0x85)
STVREN -- Stack Full/Underflow Reset Enable bit
| STVREN = OFF | 0xFE | Stack full/underflow will not cause Reset. |
| STVREN = ON | 0xFF | Stack full/underflow will cause Reset. |
LVP -- Low-Voltage ICSP Enable bit
| LVP = OFF | 0xFB | Low-voltage ICSP disabled. |
| LVP = ON | 0xFF | Low-voltage ICSP enabled. |
DEBUG -- Background Debugger Enable bit
| DEBUG = ON | 0x7F | Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug. |
| DEBUG = OFF | 0xFF | Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins. |
CONFIG5L (address:0x300008, mask:0x0F)
CP0 -- Code Protection bit
| CP0 = ON | 0xFE | Block 0 (000200-000FFFh) code-protected. |
| CP0 = OFF | 0xFF | Block 0 (000200-000FFFh) not code-protected. |
CP1 -- Code Protection bit
| CP1 = ON | 0xFD | Block 1 (001000-001FFF) code-protected. |
| CP1 = OFF | 0xFF | Block 1 (001000-001FFF) not code-protected. |
CP2 -- Code Protection bit
| CP2 = ON | 0xFB | Block 2 (002000-002FFFh) code-protected. |
| CP2 = OFF | 0xFF | Block 2 (002000-002FFFh) not code-protected. |
CP3 -- Code Protection bit
| CP3 = ON | 0xF7 | Block 3 (003000-003FFFh) code-protected. |
| CP3 = OFF | 0xFF | Block 3 (003000-003FFFh) not code-protected. |
CONFIG5H (address:0x300009, mask:0xC0)
CPB -- Boot Block Code Protection bit
| CPB = ON | 0xBF | Boot Block (000000-0001FFh) code-protected. |
| CPB = OFF | 0xFF | Boot Block (000000-0001FFh) not code-protected. |
CPD -- Data EEPROM Code Protection bit
| CPD = ON | 0x7F | Data EEPROM code-protected. |
| CPD = OFF | 0xFF | Data EEPROM not code-protected. |
CONFIG6L (address:0x30000A, mask:0x0F)
WRT0 -- Write Protection bit
| WRT0 = ON | 0xFE | Block 0 (000200-000FFFh) write-protected. |
| WRT0 = OFF | 0xFF | Block 0 (000200-000FFFh) not write-protected. |
WRT1 -- Write Protection bit
| WRT1 = ON | 0xFD | Block 1 (001000-001FFF) write-protected. |
| WRT1 = OFF | 0xFF | Block 1 (001000-001FFF) not write-protected. |
WRT2 -- Write Protection bit
| WRT2 = ON | 0xFB | Block 2 (002000-002FFFh) write-protected. |
| WRT2 = OFF | 0xFF | Block 2 (002000-002FFFh) not write-protected. |
WRT3 -- Write Protection bit
| WRT3 = ON | 0xF7 | Block 3 (003000-003FFFh) write-protected. |
| WRT3 = OFF | 0xFF | Block 3 (003000-003FFFh) not write-protected. |
CONFIG6H (address:0x30000B, mask:0xE0)
WRTC -- Configuration Register Write Protection bit
| WRTC = ON | 0xDF | Configuration registers (300000-3000FFh) write-protected. |
| WRTC = OFF | 0xFF | Configuration registers (300000-3000FFh) not write-protected. |
WRTB -- Boot Block Write Protection bit
| WRTB = ON | 0xBF | Boot Block (000000-0001FFh) write-protected. |
| WRTB = OFF | 0xFF | Boot Block (000000-0001FFh) not write-protected. |
WRTD -- Data EEPROM Write Protection bit
| WRTD = ON | 0x7F | Data EEPROM write-protected. |
| WRTD = OFF | 0xFF | Data EEPROM not write-protected. |
CONFIG7L (address:0x30000C, mask:0x0F)
EBTR0 -- Table Read Protection bit
| EBTR0 = ON | 0xFE | Block 0 (000200-000FFFh) protected from table reads executed in other blocks. |
| EBTR0 = OFF | 0xFF | Block 0 (000200-000FFFh) not protected from table reads executed in other blocks. |
EBTR1 -- Table Read Protection bit
| EBTR1 = ON | 0xFD | Block 1 (001000-001FFF) protected from table reads executed in other blocks. |
| EBTR1 = OFF | 0xFF | Block 1 (001000-001FFF) not protected from table reads executed in other blocks. |
EBTR2 -- Table Read Protection bit
| EBTR2 = ON | 0xFB | Block 2 (002000-002FFFh) protected from table reads executed in other blocks. |
| EBTR2 = OFF | 0xFF | Block 2 (002000-002FFFh) not protected from table reads executed in other blocks. |
EBTR3 -- Table Read Protection bit
| EBTR3 = ON | 0xF7 | Block 3 (003000-003FFFh) protected from table reads executed in other blocks. |
| EBTR3 = OFF | 0xFF | Block 3 (003000-003FFFh) not protected from table reads executed in other blocks. |
CONFIG7H (address:0x30000D, mask:0x40)
EBTRB -- Boot Block Table Read Protection bit
| EBTRB = ON | 0xBF | Boot Block (000000-0001FFh) not protected from table reads executed in other blocks. |
| EBTRB = OFF | 0xFF | Boot Block (000000-0001FFh) not protected from table reads executed in other blocks. |

This page generated automatically by the device-help.pl program (2013-08-01 15:50:29 UTC) from the 8bit_device.info file (rev: 1.14) of mpasmx and from the gputils source package (rev: svn 983:985). The mpasmx is included in the MPLAB X.