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- by RAM size
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- by EEPROM size

- Features
- Configuration Bits
- RAM map
- SFR map

PIC18F8723
CONFIG1H (address:0x300001, mask:0x07)
OSC -- Oscillator Selection bits
| OSC = LP | 0xF0 | LP oscillator. |
| OSC = XT | 0xF1 | XT oscillator. |
| OSC = HS | 0xF2 | HS oscillator. |
| OSC = RC | 0xF3 | External RC oscillator, CLKO function on RA6. |
| OSC = EC | 0xF4 | EC oscillator, CLKO function on RA6. |
| OSC = ECIO6 | 0xF5 | EC oscillator, port function on RA6. |
| OSC = HSPLL | 0xF6 | HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1). |
| OSC = RCIO6 | 0xF7 | External RC oscillator, port function on RA6. |
| OSC = INTIO67 | 0xF8 | Internal oscillator block, port function on RA6 and RA7. |
| OSC = INTIO7 | 0xF9 | Internal oscillator block, CLKO function on RA6, port function on RA7. |
FCMEN -- Fail-Safe Clock Monitor Enable bit
| FCMEN = OFF | 0xBF | Fail-Safe Clock Monitor disabled. |
| FCMEN = ON | 0xFF | Fail-Safe Clock Monitor enabled. |
IESO -- Internal/External Oscillator Switchover bit
| IESO = OFF | 0x7F | Two-Speed Start-up disabled. |
| IESO = ON | 0xFF | Two-Speed Start-up enabled. |
CONFIG2L (address:0x300002, mask:0x1F)
PWRT -- Power-up Timer Enable bit
| PWRT = ON | 0xFE | PWRT enabled. |
| PWRT = OFF | 0xFF | PWRT disabled. |
BOREN -- Brown-out Reset Enable bits
| BOREN = OFF | 0xF9 | Brown-out Reset disabled in hardware and software. |
| BOREN = ON | 0xFB | Brown-out Reset enabled and controlled by software (SBOREN is enabled). |
| BOREN = NOSLP | 0xFD | Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled). |
| BOREN = SBORDIS | 0xFF | Brown-out Reset enabled in hardware only (SBOREN is disabled). |
BORV -- Brown-out Voltage bits
| BORV = 0 | 0xE7 | Maximum setting. |
| BORV = 1 | 0xEF |  |
| BORV = 2 | 0xF7 |  |
| BORV = 3 | 0xFF | Minimum setting. |
CONFIG2H (address:0x300003, mask:0x1F)
WDT -- Watchdog Timer
| WDT = OFF | 0xFE | WDT disabled (control is placed on the SWDTEN bit). |
| WDT = ON | 0xFF | WDT enabled. |
WDTPS -- Watchdog Timer Postscale Select bits
| WDTPS = 1 | 0xE1 | 1:1. |
| WDTPS = 2 | 0xE3 | 1:2. |
| WDTPS = 4 | 0xE5 | 1:4. |
| WDTPS = 8 | 0xE7 | 1:8. |
| WDTPS = 16 | 0xE9 | 1:16. |
| WDTPS = 32 | 0xEB | 1:32. |
| WDTPS = 64 | 0xED | 1:64. |
| WDTPS = 128 | 0xEF | 1:128. |
| WDTPS = 256 | 0xF1 | 1:256. |
| WDTPS = 512 | 0xF3 | 1:512. |
| WDTPS = 1024 | 0xF5 | 1:1024. |
| WDTPS = 2048 | 0xF7 | 1:2048. |
| WDTPS = 4096 | 0xF9 | 1:4096. |
| WDTPS = 8192 | 0xFB | 1:8192. |
| WDTPS = 16384 | 0xFD | 1:16384. |
| WDTPS = 32768 | 0xFF | 1:32768. |
CONFIG3L (address:0x300004, mask:0xF3)
MODE -- Processor Data Memory Mode Select bits
| MODE = EM | 0xFC | Extended Microcontroller mode. |
| MODE = MPB | 0xFD | Microprocessor with Boot Block mode. |
| MODE = MP | 0xFE | Microprocessor mode. |
| MODE = MC | 0xFF | Microcontroller mode. |
ADDRBW -- Address Bus Width Select bits
| ADDRBW = ADDR8BIT | 0xCF | 8-bit Address Bus. |
| ADDRBW = ADDR12BIT | 0xDF | 12-bit Address Bus. |
| ADDRBW = ADDR16BIT | 0xEF | 16-bit Address Bus. |
| ADDRBW = ADDR20BIT | 0xFF | 20-bit Address Bus. |
DATABW -- Data Bus Width Select bit
| DATABW = DATA8BIT | 0xBF | 8-bit External Bus mode. |
| DATABW = DATA16BIT | 0xFF | 16-bit External Bus mode. |
WAIT -- External Bus Data Wait Enable bit
| WAIT = ON | 0x7F | Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits. |
| WAIT = OFF | 0xFF | Wait selections are unavailable for table reads and table writes. |
CONFIG3H (address:0x300005, mask:0x83)
CCP2MX -- CCP2 MUX bit
| CCP2MX = PORTBE | 0xFE | ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. |
| CCP2MX = PORTC | 0xFF | ECCP2 input/output is multiplexed with RC1. |
ECCPMX -- ECCP MUX bit
| ECCPMX = PORTH | 0xFD | ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively. |
| ECCPMX = PORTE | 0xFF | ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively. |
LPT1OSC -- Low-Power Timer1 Oscillator Enable bit
| LPT1OSC = OFF | 0xFB | Timer1 configured for higher power operation. |
| LPT1OSC = ON | 0xFF | Timer1 configured for low-power operation. |
MCLRE -- MCLR Pin Enable bit
| MCLRE = OFF | 0x7F | RG5 input pin enabled; MCLR disabled. |
| MCLRE = ON | 0xFF | MCLR pin enabled; RG5 input pin disabled. |
CONFIG4L (address:0x300006, mask:0x85)
STVREN -- Stack Full/Underflow Reset Enable bit
| STVREN = OFF | 0xFE | Stack full/underflow will not cause Reset. |
| STVREN = ON | 0xFF | Stack full/underflow will cause Reset. |
LVP -- Single-Supply ICSP Enable bit
| LVP = OFF | 0xFB | Single-Supply ICSP disabled. |
| LVP = ON | 0xFF | Single-Supply ICSP enabled. |
BBSIZ -- Boot Block Size Select bits
| BBSIZ = BB2K | 0xCF | 1K word (2 Kbytes) Boot Block size. |
| BBSIZ = BB4K | 0xDF | 2K words (4 Kbytes) Boot Block size. |
| BBSIZ = BB8K | 0xEF | 4K words (8 Kbytes) Boot Block size. |
XINST -- Extended Instruction Set Enable bit
| XINST = OFF | 0xBF | Instruction set extension and Indexed Addressing mode disabled (Legacy mode). |
| XINST = ON | 0xFF | Instruction set extension and Indexed Addressing mode enabled. |
DEBUG -- Background Debugger Enable bit
| DEBUG = ON | 0x7F | Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug. |
| DEBUG = OFF | 0xFF | Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins. |
CONFIG5L (address:0x300008, mask:0xFF)
CP0 -- Code Protection bit Block 0
| CP0 = ON | 0xFE | Block 0 (000800, 001000 or 002000-003FFFh) code-protected. |
| CP0 = OFF | 0xFF | Block 0 (000800, 001000 or 002000-003FFFh) not code-protected. |
CP1 -- Code Protection bit Block 1
| CP1 = ON | 0xFD | Block 1 (004000-007FFFh) code-protected. |
| CP1 = OFF | 0xFF | Block 1 (004000-007FFFh) not code-protected. |
CP2 -- Code Protection bit Block 2
| CP2 = ON | 0xFB | Block 2 (008000-00BFFFh) code-protected. |
| CP2 = OFF | 0xFF | Block 2 (008000-00BFFFh) not code-protected. |
CP3 -- Code Protection bit Block 3
| CP3 = ON | 0xF7 | Block 3 (00C000-00FFFFh) code-protected. |
| CP3 = OFF | 0xFF | Block 3 (00C000-00FFFFh) not code-protected. |
CP4 -- Code Protection bit Block 4
| CP4 = ON | 0xEF | Block 4 (010000-013FFFh) code-protected. |
| CP4 = OFF | 0xFF | Block 4 (010000-013FFFh) not code-protected. |
CP5 -- Code Protection bit Block 5
| CP5 = ON | 0xDF | Block 5 (014000-017FFFh) code-protected. |
| CP5 = OFF | 0xFF | Block 5 (014000-017FFFh) not code-protected. |
CP6 -- Code Protection bit Block 6
| CP6 = ON | 0xBF | Block 6 (01BFFF-018000h) code-protected. |
| CP6 = OFF | 0xFF | Block 6 (01BFFF-018000h) not code-protected. |
CP7 -- Code Protection bit Block 7
| CP7 = ON | 0x7F | Block 7 (01C000-01FFFFh) code-protected. |
| CP7 = OFF | 0xFF | Block 7 (01C000-01FFFFh) not code-protected. |
CONFIG5H (address:0x300009, mask:0xC0)
CPB -- Boot Block Code Protection bit
| CPB = ON | 0xBF | Boot Block (000000-0007FFh) code-protected. |
| CPB = OFF | 0xFF | Boot Block (000000-0007FFh) not code-protected. |
CPD -- Data EEPROM Code Protection bit
| CPD = ON | 0x7F | Data EEPROM code-protected. |
| CPD = OFF | 0xFF | Data EEPROM not code-protected. |
CONFIG6L (address:0x30000A, mask:0xFF)
WRT0 -- Write Protection bit Block 0
| WRT0 = ON | 0xFE | Block 0 (000800, 001000 or 002000-003FFFh) write-protected. |
| WRT0 = OFF | 0xFF | Block 0 (000800, 001000 or 002000-003FFFh) not write-protected. |
WRT1 -- Write Protection bit Block 1
| WRT1 = ON | 0xFD | Block 1 (004000-007FFFh) write-protected. |
| WRT1 = OFF | 0xFF | Block 1 (004000-007FFFh) not write-protected. |
WRT2 -- Write Protection bit Block 2
| WRT2 = ON | 0xFB | Block 2 (008000-00BFFFh) write-protected. |
| WRT2 = OFF | 0xFF | Block 2 (008000-00BFFFh) not write-protected. |
WRT3 -- Write Protection bit Block 3
| WRT3 = ON | 0xF7 | Block 3 (00C000-00FFFFh) write-protected. |
| WRT3 = OFF | 0xFF | Block 3 (00C000-00FFFFh) not write-protected. |
WRT4 -- Write Protection bit Block 4
| WRT4 = ON | 0xEF | Block 4 (010000-013FFFh) write-protected. |
| WRT4 = OFF | 0xFF | Block 4 (010000-013FFFh) not write-protected. |
WRT5 -- Write Protection bit Block 5
| WRT5 = ON | 0xDF | Block 5 (014000-017FFFh) write-protected. |
| WRT5 = OFF | 0xFF | Block 5 (014000-017FFFh) not write-protected. |
WRT6 -- Write Protection bit Block 6
| WRT6 = ON | 0xBF | Block 6 (01BFFF-018000h) write-protected. |
| WRT6 = OFF | 0xFF | Block 6 (01BFFF-018000h) not write-protected. |
WRT7 -- Write Protection bit Block 7
| WRT7 = ON | 0x7F | Block 7 (01C000-01FFFFh) write-protected. |
| WRT7 = OFF | 0xFF | Block 7 (01C000-01FFFFh) not write-protected. |
CONFIG6H (address:0x30000B, mask:0xE0)
WRTC -- Configuration Register Write Protection bit
| WRTC = ON | 0xDF | Configuration registers (300000-3000FFh) write-protected. |
| WRTC = OFF | 0xFF | Configuration registers (300000-3000FFh) not write-protected. |
WRTB -- Boot Block Write Protection bit
| WRTB = ON | 0xBF | Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected. |
| WRTB = OFF | 0xFF | Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected. |
WRTD -- Data EEPROM Write Protection bit
| WRTD = ON | 0x7F | Data EEPROM write-protected. |
| WRTD = OFF | 0xFF | Data EEPROM not write-protected. |
CONFIG7L (address:0x30000C, mask:0xFF)
EBTR0 -- Table Read Protection bit Block 0
| EBTR0 = ON | 0xFE | Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks. |
| EBTR0 = OFF | 0xFF | Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks. |
EBTR1 -- Table Read Protection bit Block 1
| EBTR1 = ON | 0xFD | Block 1 (004000-007FFFh) protected from table reads executed in other blocks. |
| EBTR1 = OFF | 0xFF | Block 1 (004000-007FFFh) not protected from table reads executed in other blocks. |
EBTR2 -- Table Read Protection bit Block 2
| EBTR2 = ON | 0xFB | Block 2 (008000-00BFFFh) protected from table reads executed in other blocks. |
| EBTR2 = OFF | 0xFF | Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks. |
EBTR3 -- Table Read Protection bit Block 3
| EBTR3 = ON | 0xF7 | Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks. |
| EBTR3 = OFF | 0xFF | Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks. |
EBTR4 -- Table Read Protection bit Block 4
| EBTR4 = ON | 0xEF | Block 4 (010000-013FFFh) protected from table reads executed in other blocks. |
| EBTR4 = OFF | 0xFF | Block 4 (010000-013FFFh) not protected from table reads executed in other blocks. |
EBTR5 -- Table Read Protection bit Block 5
| EBTR5 = ON | 0xDF | Block 5 (014000-017FFFh) protected from table reads executed in other blocks. |
| EBTR5 = OFF | 0xFF | Block 5 (014000-017FFFh) not protected from table reads executed in other blocks. |
EBTR6 -- Table Read Protection bit Block 6
| EBTR6 = ON | 0xBF | Block 6 (018000-01BFFFh) protected from table reads executed in other blocks. |
| EBTR6 = OFF | 0xFF | Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks. |
EBTR7 -- Table Read Protection bit Block 7
| EBTR7 = ON | 0x7F | Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks. |
| EBTR7 = OFF | 0xFF | Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks. |
CONFIG7H (address:0x30000D, mask:0x40)
EBTRB -- Boot Block Table Read Protection bit
| EBTRB = ON | 0xBF | Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks. |
| EBTRB = OFF | 0xFF | Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks. |

This page generated automatically by the device-help.pl program (2013-08-01 15:50:29 UTC) from the 8bit_device.info file (rev: 1.14) of mpasmx and from the gputils source package (rev: svn 983:985). The mpasmx is included in the MPLAB X.