Copyright: Copyright 1993 Intel Corp. World rights reserved.


Model LP386SX-20 Informational Help File - Main Menu

Model LP386SX-20 Technical Information is organized under the following subjects:

Intel Product Update Bulletin (iPUB)	General Product Information

System Product History	Product Order Codes

Board Product History	Regulatory Certifications

BIOS History Menu

Orderable Spare Parts List

Technical Product Summary Information

Introduction to the Model LP386SX-20

System Features Menu

Additional Information


Introduction to the Model LP386SX-20
Introduction

The INTEL LP386SX-20 is a compact, reliable, and cost effective high-performance microcomputer system.  The LP386SX-20 microcomputer, unlike IBM's Personal Computer AT (PC/AT), has the following features and functions integrated into the system baseboard: keyboard and auxiliary device (mouse) controller, the video graphics array (VGA & Super VGA) video controller, the floppy disk controller (FDC), an AT (IDE) interface connector for the fixed disk drive, a serial port, and parallel port controller.  The LP386SX-20 microcomputer has three IBM PC/AT (ISA) 16-bit compatible l/O bus connectors for optional feature expansions such as memory expansion, network support, add-in video card or other customized features.  The Intel LP386SX-20 microcomputer was designed to be a low cost, high quality system integrating onboard system features and functions that normally required an add-in card.  This will simplify the OEM's system integration task, provide greater reliability, frees up additional ISA slots, reduces power requirements, as well as enhancing performance through the optimization of new integrated features and functions.

Applications where the LP386SX-20 microcomputer excels include networked office workstations, remote terminals, as a multifunction client system, and in OEM applications such as process control or instrumentation.  The LP386SX-20 Microcomputer was designed and built to be reliable using state of the art components and manufacturing techniques.  This document outlines the features and specifications of the LP386SX-20 Microcomputer enabling a reader to make informed decisions about the system's limits and capabilities with respect to the customer's application.  The system can effectively serve applications ranging from a slave terminal in a central host system, through an intelligent workstation in a local area network (LAN), to a high-performance general-purpose single-user personal computer.  The LP386SX-20 microcomputer is fully IBM PC/AT compatible and supports Microsoft's MS-DOS as well as other operating environments such as XENIX, UNIX System V/386, and Microsoft's Windows 3.0.


Model LP386SX-20 System Features Menu

Power Supply	Disk Drives

Keyboard and Mouse	I/O Ports

TOPCAT Chip Set	ISA Bus Slots

System Memory	CMOS RAM and Real-Time Clock

Security	"De-turbo" Feature

Video Subsystem	Floppy Disk Controller

Fixed-Disk Interface	Serial Port Controller

Parallel Port Controller	System Timers

DMA Controller	Phoenix Technologies BIOS

Power-On Self Test


Power Supply Features
Power Supply

The power supply is contained inside of the system unit to provide the power for the system board, the adapters that plugged into the I/O expansion slot board, the floppy disk drive(s), the fixed-disk drive, the keyboard and the auxiliary device, etc. - the primary power to the monitor is provided externally.  The power supply used in the system unit is a 114 Watt multiple output switching power supply, packaged in a metal enclosure.  The input voltage level may be selected by a switch to operate either at 115 VAC or 230 VAC.

Also see the following topics for further information regarding the power supply:

Power Supply Input

Power Supply Output


Power Supply Input

The power supply operates with two ranges of input voltages which can be selected by a slide switch located on the inner side of the power supply.  The following table shows the input requirements for both ranges:

Input Voltage	Maximum Current	Frequency
90-135 VAC	5.0 Amps	50/60 Hz
180-270 VAC	2.5 Amps	50/60 Hz

In-rush Current: 50A peak, full load, cold start at 25 degrees C.

Hold-Up Time: Greater than 20mS at full load, 115 VAC or 230 VAC input.

Input Protection

The power supply utilizes a 5 Amp fuse to protect against over-current from the external power input.  This fuse is located on the rear of the power supply unit which is accessible from the rear of the system.


POWER SUPPLY OUTPUT

The following table lists the DC output ratings for the HD120 power supply:

DC Voltage	Max. Continuous  Current	Minimum  Load	Peak Surge  for 10 Seconds	Regulation  +%       -%	Ripple & Noise (mVp-p)
+  5 Volts	13.5 Amps	2.0 Amps		5               5	100
-   5 Volts	0.3 Amps	-		5               5	150
+ 12 Volts	3.5 Amps	-	6.0 Amps	5                5	150
-  12  Volts	0.3 Amps	-		5                5	200
AC Output

This output is used for the monitor attached to the system:

- 115V Setting : 2.0 Amps / 115 Volts

- 230V Setting : 1.0 Amps / 230 Volts

Output Protection

A short circuit placed on any DC output (between outputs or between an output and DC return) and an overvoltage fault (internal to the power supply) latches all DC outputs into a shut down state with no damage to the power supply.

Overvoltage : 5.6 Volts to 7.0 Volts on +5V rail

Overcurrent : The power supply shall shut down all DC output when main output is overloaded to the extent that is absolute voltage drops below 2.5 Volts.  The power supply logic shall latch into the off state requiring a power on cycle to be performed by the operator.  The power supply will turn off within 20 mS of the occurrence of the overload.  An over current on any output shall cause no damage to the unit.  If either of these shut down states is actuated, the power supply returns to normal operation only after the fault has been removed and the power switch has been turned off for at least 3 seconds.


Disk Drive Support
Disk Drives

The following storage devices are supported by the LP386SX-20:

Internal:

3.5" floppy disk drive (1.44Mb or 720Kb capacity)

3.5" half-height fixed-disk drive (52Mb, 105Mb, etc.) using the IDE PC/AT interface connector on the system baseboard.

Internal or External:

SCSI/ESDI fixed disk drives using an add-in controller card plugged into one of the I/O expansion slots.

When changing fixed-disk drives, be sure to note the drive type/characteristics for entry into CMOS via the SETUP utility.  If the TYPE information for the fixed-disk is set incorrectly, it is possible that the data contained on the disk could be corrupted.  The drive TYPE can be confirmed by consulting the manual for the fixed-disk in question.


Keyboard and Mouse Support
Keyboard and Mouse

The LP386SX-20 is designed to use a standard 101-key keyboard and PS/2-compatible mouse or pointing device.  The keyboard and auxiliary devices are connected to the system via 6-pin PS/2-style DIN connectors located on the rear of the system unit.

The keyboard/auxiliary device controller used on the system baseboard is compatible with the Intel 8042 or 8742 chip.  The auxiliary device may be any type of non +/-12 V serial input device that is compatible with the keyboard controller interface.  The keyboard controller takes the serial data from the keyboard or auxiliary device, checks the parity, translates keyboard scan codes, and puts the data to the system as a byte of data at I/O address 60H.  The controller can interrupt the system when data is available or can wait for the microprocessor to poll its status register.

The keyboard "click" volume can be adjusted by depressing the CTRL, SHIFT, and + keys simultaneously.  The keyboard volume will increase each time this key combination is depressed up to a maximum level.  When the maximum level is reached, the volume will return to a minimum level, after which it will begin increasing again.


I/O Ports

One serial port and one parallel port are provided on the system baseboard.  The serial port is RS-232C compatible and is programmable to the required baud rate and framing characteristics of attached communications devices.  The serial port is asynchronous and bi-directional and uses a 9-pin male-type D-shell interface connector.  The devices that can be attached to the serial port include the following:

Communication terminal to a host system

Serial printer

Data modem

Mouse

The interface for the Centronics-compatible parallel port is a 25-pin female-type D-shell connector.  Devices that can be attached to the parallel port include printers and security keys.


Phoenix Technologies BIOS
Phoenix Technologies System BIOS

The Intel LP386SX-20 microcomputer uses the Phoenix Technologies ROM BIOS Plus version 1.10 17.T0, or greater which provides IBM PS/2 compatibility.  The system BIOS is located in two socketed 27C512 (64Kb) EPROMs located at U9 and U10 on the baseboard.  System ROM resides at F0000H to FFFFFH, and the onboard video ROM (including Power-On Self Test and SETUP programs) resides at E0000H to EFFFFH.

A SETUP option is available that allows the system and on-board video BIOS to be copied from on-board ROM into onboard RAM for faster access.  This option is referred to as "shadowing".

When the ROM BIOS is copied into RAM, the CPU accesses the BIOS at the same speed it accesses other on-board RAM.  The system board architecture makes sure the ROM BIOS copied into the RAM is write-protected to prevent inadvertant overwriting of BIOS information.


TOPCAT PC/AT Chip Set

Intel 82343 PC/AT System Controller

Use of the Intel 82343 (VLSI 82C320) 20MHz System Controller provides many benefits in a highly integrated package.  Besides providing much of the support for some of the other system features it provides the ability to re-map bad blocks of system memory found during the POST sequence and still allow the operating system to view RAM as a contiguous address space.  The 82C320 provides Lotus-Intel-Microsoft Expanded Memory Specification Version 4.0 (LIM EMS) support in hardware.  Hardware implementations of the LIM EMS are typically faster than using software emulation.  RAM shadowing in 16Kb increments is supported which will help alleviate RAM availability problems in the address range from A0000H to FFFFFH (640Kb to 1Mb) and staggers the RAM refreshes by banks to reduce EMI/RFI emissions.  Additional enhanced PC/AT features supported include a fast reset CPU, fast gate A20, and optional disable for the NPX reset signals.

Intel 82344 PC/AT Bus Controller

The Intel 82344 (VLSI 82C331) PC/AT Bus Controller provides enhanced versions of all the standard PC/AT peripherals including: 2-8259 interrupt controllers, 2-8237 DMA controllers, 1-8254 programmable timer/counter, the RTC and 128 bytes of CMOS memory.  This device also provides 10-bit (by default) or 16-bit I/O address decoding via software control for systems that need the full non-overlapping I/O address range, and a "bus quiet" feature which retains the previous logic state of ISA bus data and control lines when no valid bus accesses are occurring.


ISA Bus Slots

Three 16-bit ISA slots are provided for system expansion, 8-bit ISA bus cards can also be used as long as they are not "drop cards".  The LP386SX-20 will not accept any 32-bit bus cards.  The three 16-bit ISA slots are horizontally mounted on a riser card that plugs into a single vertical 16-bit ISA connector on the baseboard.


System Memory

Up to 32 Megabytes of on-board memory can be installed using SIMMs that include 256K x 9, 1 MB x 9 or 4MB x 9 DRAMs.  SIMMs of two different DRAM sizes can be mixed within a single LP386SX-20 as long as the SIMMs are installed in banks (pairs) of the same type (size).  The system BIOS in the LP386SX-20 automatically sizes memory and initializes the Intel 82343 System Controller.

The LP386SX-20 assumes the use of 80 nSec Fast Page-Mode DRAM accesses to the on-board memory to attain an average of less than 0.3 386SX wait states.  Onboard memory supports parity checking (a high and low parity bit for each 16-bit word can be enabled/disabled via software using I/O port 79) but, Error Checking and Correction (ECC) is not supported.

The re-mapping of unused DRAM memory space between 640Kb to 1Mb into higher addresses is supported to increase the available extended memory.  This is allowed when there is not 16Mb of on-board Extended memory and when all shadowing is disabled via SETUP.

Also see the following topics for more information on the memory subsystem:

ROM Subsystem	RAM Subsystem

EMS Support	CMOS RAM

DMA Controller	Memory Map


CMOS RAM and Real-Time Clock

The Real Time Clock (RTC) can be set via the BIOS SETUP program.  The RTC and System timer both have sufficiently tight tolerances to support average clock error rates of less than 8 minutes per year, worst case at 16 minutes/year.  CMOS memory supports the standard 64-byte battery-backed RAM and an additional 64-bytes of battery backed RAM - all of the CMOS RAM data area is reserved for BIOS use.

The real-time clock and 128 bytes of non-volatile CMOS RAM are provided by the 82C331 component (Motorola MC146818-compatible).  The internal clock circuitry uses 14 bytes of this memory, and the rest is allocated to configuration and system status information.

The industry standard 3.6 volt lithium battery (Tadiran #TL-5242/w) is used to power/back up the CMOS RAM when the LP386SX-20 is powered down.  A 4.5 volt alkaline battery can also be used, but the use of batteries rated greater than 4.5 volts may damage the baseboard.  These batteries are attached to the system with a VELCRO-brand strip to the back of the ISA riser card for easy replacement.  The expected life of the battery is greater than 3 years.


Security

There are two methods used to secure the LP386SX-20 Microcomputer.  The first is the standard PC/AT mechanical keylock.  When activated, the keylock locks out all keyboard input - this is not a chassis lock and there is only 1 key.

The second method to prevent unauthorized use of the LP386SX-20 is by CMOS password at power on.  If the CMOS password is set the LP386SX-20 will prompt the user for a password each time the system is booted.  The CMOS password can be set, changed, or deleted by following the steps below.

1.	To set the CMOS password, insert the Startup diskette into drive A, turn the LP386SX-20 Microcomputer on, select Set Feature from the main menu, then select Set Power-On Password and follow the instructions on the screen.

2.	To change the power-on CMOS password, turn the LP386SX-20 microcomputer on, type your current CMOS password at the password prompt, then press the key just above the right ALT key (/).  Now type in your new password and press the ENTER key.  The CMOS password is now changed.

3.	To remove or delete the existing CMOS password, turn the LP386SX-20 microcomputer on, type your current CMOS password at the password prompt, then press the key just above the right ALT key (/), then press the ENTER key.  The CMOS password is now deleted.  If the user forgets the CMOS password and wants to reset the CMOS password, the user must disconnect the LP386SX-20 system battery and after about 24 hours the CMOS password, as well the rest of CMOS, will need to be reset.

Once the power-on CMOS password is set, the LP386SX-20 will prompt the user each time the system is rebooted.  To be able to use the system the user must type the correct password and press the ENTER key.  If the user mistypes the CMOS password the system will display "Illegal Password" and the user will have 5 attempts to re-enter the password before the LP386SX-20 will have to be rebooted.


"De-turbo" Feature

The LP386SX-20 microcomputer provides a feature ("De-turbo") that reduces the effective CPU speed to be compatible with some older applications and copy protection methods.  There are two methods available to lower the normal CPU speed from 20MHz to approximately 8MHz.  One way is to set the speed via the CPU Speed ("SLOW" or "FAST") option in the SETUP utility.  The second method is temporary and allows the user to dynamically switch speeds via the keyboard.  To toggle the operating speed from the keyboard, press the CTRL, SHIFT, and NUMLOCK keys simultaneously.


Video Subsystem

The LP386SX-20 video is produced by the Western Digital Video Graphics Array (VGA) controller, WD90C11, and the associated circuitry consisting of the video memory (512Kb), a WD90C61 video clock generator, and a video digital-to-analog converter (DAC).  The RGB (Red, Green and Blue) outputs from the video DAC drive analog displays with 31.5KHz horizontal deflection for standard PS/2 (analog) monitors.  Monochrome Display Adapter (MDA), IBM Color Graphics Adapter (CGA), and IBM Enhanced Graphics Adapter (EGA) video modes are all supported.  Four 256K x 4-bit 70 nSec Fast Page-Mode DRAMs are used to provide the 512Kb of video RAM.  This provides for a maximum resolution of 1024 x 768 pixels with 16 displayed colors (interlaced).  The 512Kb display RAM is paged into 128K of RAM located between A0000H and BFFFFH but accessible only via VGA controller registers.  The industry standard VGA modes available through the Western Digital Video BIOS are:

IBM compatible modes

320 x 200 graphics with 256 colors

640 x 480 graphics with both 2 and 16 colors

80 x 25 alphanumeric with both 16 colors and monochrome

40 x 25 alphanumeric with 16 colors

Enhanced modes (with 512Kb video memory)

1024 x 768 graphics with 2 or 4 colors

1024 x 768 graphics with 16 colors, interlaced mode

800 x 600 graphics with 16 colors

800 x 600 graphics with 256 colors

640 x 400 graphics with 256 colors

640 x 480 graphics with 256 colors

132 x 25 or 132 x 43 alphanumeric with colors

Also see the following topics for more information on the video subsystem:

Video Interface	Graphics Modes

Alphanumeric Modes	Video Connector


Video Interface

The WD90C11 VGA controller interfaces with the CPU and video memory.  Display data passes through the VGA controller when the system microprocessor writes to or reads from video memory.  The VGA controller controls the arbitration for memory between the microprocessor and the cathode ray tube (CRT) controller within the VGA controller.

The VGA controller controls video memory addressing; the start address of the video memory is programmable to three different addresses for compatibility with previous video adapters.  The VGA controller formats the information stored in video memory into an 8-bit digital value that is sent to the video DAC.  This 8-bit data can access to a maximum of 256 registers inside the video DAC.  Each register inside the video DAC contains a color value that is selected from a choice of over 256K colors.  The video DAC outputs three analog color signals (red, green, and blue - RGB) that are sent to the analog display monitor through the connector.  The monochrome display uses only the green analog output that is used to determine the shade of gray.  The on-board VGA controller can be enabled or disabled by using the jumper switch J3 on the baseboard (IN = Enable, OUT = Disable).  Depending on the type of the video adapters used in the system, the switch must be properly set as follows:

Type of Video Adapter	BIOS Used	Switch Setting
On-board VGA controller	On-board BIOS	IN
Monochrome Display Adapter	None	IN
Color/Graphics Adapter	None	IN
Enhanced Graphics Adapter	Adapter BIOS	OUT
Other VGA Adapter	Adapter BIOS	OUT

The VGA controller's DRAM and bus interface timing logic operates at the rate of 37.585 MHz clock with 80ns DRAM being used for the video memory.  Four clocks from the WD90C61 clock generator provide the dot rate for the video display; 28.189 MHz for alphanumeric modes, 25.057 MHz for graphics modes, and 36.242 MHz and 44.744 MHz for enhanced VGA modes.  The BIOS selects these clocks by setting the bits in a sequencer register and Paradise registers whenever a video mode is set.  The digital video output is sent to the video digital-to-analog converter (DAC) which contains a color look-up table.  Three analog signals (red, green, and blue) are output from the video DAC to the CRT display.  The 'sync' signals to the monitor are TTL levels and the analog video signals are 0 to 0.7 volts.


Graphics Modes
Graphic Modes of Operation

Mode	Resolution	Video Std.	Colors	Memory
4,5	320x200	CGA	4	256KB
		EGA	4 out of 64
		MCGA	4 out of 256
		VGA	4 out of 256
6	640x200	CGA	2	256KB
		EGA	2 out of 64
		MCGA	2 out of 256K
		VGA	2 out of 256K
D	320x200	EGA	16 out of 64	256KB
		VGA	16 out of 256K
E	640x200	EGA	16 out of 64	256KB
		VGA	16 out of 256K
F	640x350	EGA	Monochrome	256KB
		VGA	Monochrome
10	640x350	EGA	16 out of 64	256KB
		VGA	16 out of 256K
11	640x480	MCGA	2 out of 256K	256KB
		VGA	2 out of 256K
12	640x480	VGA	16 out of 256K	256KB
13	320x200	MCGA	256 out of 256K	256KB
		VGA	256 out of 256K
58	800x600	Enhanced	16 out of 256K	256KB
59	800x600	Enhanced	Monochrome	256KB
5A	1024x768	Enhanced	2 out of 256	256KB
5B	1024x768	Enhanced	4 out of 256	256KB
5C	800x600	Enhanced	256 out of 256	512KB
5D	1024x768	Enhanced	16 out of 256	512KB
5E	640x400	Enhanced	256 out of 256	256KB
5F	640x480	Enhanced	256 out of 256	512KB
6A	800x600	Enhanced	16 out of 256K (*)	256KB
6B	800x600	Enhanced	Monochrome (*)	256KB

(*) VESA modes.


Alphanumeric Modes
Alphanumeric Modes of Operation

Mode	Rows	Columns	Video Std.	Display Area	Resolution	Colors
0,1	25	40	CGA	8x8	320x200	16
			EGA	8x14	320x350	16 out of 64
			MCGA	8x16	320x400	16 out of 256K
			VGA	9x16	360x400	16 out of 256K
2,3	25	80	CGA	8x8	640x200	16
			EGA	8x14	640x350	16 out of 64
			MCGA	8x16	640x400	16 out of 256K
			VGA	9x16	720x400	16 out of 256K
7	25	80	MDA	9x14	720x350	Monochrome
			EGA	9x14	720x350	Monochrome
			VGA	9x16	720x400	Monochrome
54	43	132	Enhanced	7x9	924x387	Color
55	25	132	Enhanced	7x16	924x400	Color
56	43	132	Enhanced	7x9	924x387	Monochrome
57	25	132	Enhanced	7x16	924x400	Monochrome


Video Connector

A standard PS/2 15-pin analog VGA connector is provided on the back of the LP386SX-20, this is driven by a 50MHz Inmos 171 RamDAC.  If a nine-pin TTL video connector is required for monochrome, CGA, or EGA style monitor an add-in video adapter card must be used for the nine pin connector.

Pin No.	I/O	Signal Name	Monochrome	Color
1	O	Red Video	Not Used	Red Video
2	O	Green Video	Monochrome	Green Video
3	O	Blue Video	Not Used	Blue Video
4	NA	Reserved
5	NA	Digital Ground
6	NA	Analog Ground
7	NA	Analog Ground
8	NA	Analog Ground
9	NA	Reserved
10	NA	Digital Ground
11	NA	Reserved
12	NA	Reserved
13	O	Horizontal Sync	HSYNC	HSYNC
14	0	Vertical Sync	VSYNC	VSYNC
15	NA	Reserved


FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) is integrated on the baseboard.  The National Semiconductor Corporation's Super I/O PC87310 which incorporates the floppy disk controller functions is used.  It can support two floppy disk drives using a daisy-chain cable, which can be one of the following:

Type of FDDrive	Storage Capacity (Formatted)
3.5"  DS, HD	1.44 MBytes
3.5"  DS, DD	720 KBytes
5.25" DS, HD	1.2 MBytes
5.25" DS, HD	360 KBytes

The on-board floppy disk controller can be enabled or disabled by the SETUP utility or by using hardware jumper J9 (IN : Enable, OUT : Disable).  If the latter method is used, all functions of Super I/O PC87310 will be disabled (FDC, IDE Interface, SIO, and PIO).  When the on-board floppy disk controller is disabled, then another floppy disk controller card must be plugged into one of the I/O expansion slots to use the floppy disk drives.  The connector on the system board for the attachment of one or two floppy disk drives is a 34-pin connector.  All signals and data are transmitted from and to the drive through this connector.


Fixed Disk Interface
FIXED-DISK INTERFACE

The fixed-disk drive AT interface circuitry is provided by using IDE-40 connector (IDE : Intelligent Drive Electronics). This circuitry consists of the 40-pin connector connected to a RLL type fixed-disk drive, decoding logic for the Chip Select signals, and buffering components.

The SETUP utility enables or disables the AT interface logic located on the baseboard. The onboard IDE interface circuit is enabled by setting "ON Board HDD" option to "Enabled" in SETUP or by setting hardware jumper J9 (IN : Enable, OUT : Disable).  When other Fixed-Disk Controller and other types of Fixed-Disk Drives (SCSI/ESDI) are used in the system, the option should be set to "Disabled" and the cable which is plugged into the connector on the system board should be removed.


SERIAL PORT CONTROLLER

The serial port is controlled by a serial communication controller in the SUPER I/O PC87310 Chip.  This port is programmable and supports asynchronous communications.  The controller automatically adds and removes start, step, and parity bits.  A programmable baud-rate generator allows operation from 50 to 56,000 bits-per-second (bps).  The port supports 5-, 6-, 7-and 8-bit characters with 1, 1.5, or 2 stop bits.  A prioritized interrupt system controls transmit, receive, error, and line status as well as data-set interrupts.

The serial port is RS-232C compatible and bi-directional port.  This port is used to communicate with an serial printer, plotter, modem, terminal, or other types of peripheral device.  The PC87310 supports basically two serial ports, but the system board provides only one 9-Pin serial port connector.  With programming, the serial port can be enabled or disabled and can be assigned as one of two logical devices: COM1 or COM2.  Selection is accomplished by programming the bits 4-2 of SUPER I/O configuration register (I/O address 03F3 hex).  It can be controlled by SETUP utility or direct I/O access to address hex 03F3.  The bit definition of configuration register for the serial port is shown below:

			FUNCTION
Bit 4	Bit 3	Bit 2	UART 1	UART 2
0	0	0	COM1 (3F8-3FF)	COM2 (2F8-2FF)
0	0	1	Disabled	COM2
0	1	0	COM1	Disabled
0	1	1	Disabled	Disabled
1	0	0	COM2	COM1
1	0	1	Disabled	COM1
1	1	0	COM2	Disabled
1	1	1	Disabled	Disabled
UART2 is not available - the system board supports UART1 only.


Parallel Port Connector
PARALLEL PORT CONTROLLER

The parallel port allows the connection of various devices that transfer 8 bits of parallel data at standard TTL level.  A 25-pin, D-shell connector for the parallel port is provided at the rear of the system unit.  This port is write-only port that supports the parallel Centronics type printer.  By using the SETUP utility, the parallel port on the system board can be enabled or disabled and can be assigned as one of three logical devices: LPT1, LPT2 or LPT3.  Selection is accomplished by selecting the "Onboard LPT" menu.  When on-board parallel port is used, the hardware jumper J9 must be connected so as to enable SUPER I/O Chip operation, which provides FDC, HDD Interface, and Serial Port functions.

The I/O address space for each parallel port is as follows:

Function	I/O Address Range
LPT1	03BC-03BF
LPT2	0378 - 037F
LPT3	0278 - 027F


Read-Only Memory (ROM) Subsystem

The system board ROM subsystem consists of two 64K-by-8-bit ROM modules in a 64K-by-16-bit arrangement. The code for odd and even addresses resides in separate modules. ROM is assigned at the top of the first and last 1Mb address space (0E0000 hex and FE0000).  Note that the ROM locations are not parity-checked.

In the system ROM, the following functions are included:

System BIOS including Power-On Self Test

SETUP Utility

Video BIOS for on-board VGA (Video Graphics Array)

The DRAM controller provides several address mapping options to improve performance and allow flexibility in the system memory size and configuration.  These options include ROM shadowing and mapping up to 384KB addresses above the top of physical memory into physical addresses.  The selection of these options is done via programming of the memory configuration registers via the SETUP configuration utility.

Shadowing refers to copying data from slow memory devices like ROM into DRAM to speed up memory accesses.  The memory controller has built-in support for shadowing two different areas of memory: BIOS ROM and Adapter ROM.  Roll address mapping is a method of utilizing DRAM memory space that may not otherwise be accessible.  If shadowing is not selected (if the memory map is 1F or 1E), because any addresses in these areas will access ROM or system video RAM and any local DRAM in this address range cannot be directly accessed, the memory controller can re-map or "roll" 384KB memory ranging from 640KB to 1MB above the top of the physical memory to use as the extended memory.  This operation can be done only when the memory map is 1F (1MB installed using four 256KB SIMM modules) or 1E (2MB installed using two 1MB SIMM modules).


Random Access Memory (RAM) Subsystem

The RAM subsystem starts at the first address, hex 000000, of the 16 MB address space.  The memory configurations and size are dependent on the DRAM type.  The DRAM types that can be used on the system board are as follows:

256K-by-9-bit SIMM (Single In-line Memory Module) package

1M-by-9-bit SIMM package

4M-by-9-bit SIMM package

The modules used in multiple banks can consist of all the same type DRAMs or a mixture of two different types (256Kb, 1Mb, or 4Mb).  There are eight SIMM sockets (U1 - U8) on the system board.

The microprocessor operates at 20 MHz with zero wait state (Fast mode) or 8MHz clock rate ("De-turbo" mode) for CPU cycles.  The fast mode is used for the best performance and the "De-turbo" mode is used for compatibility with older 80286 programs that contain software timing loops.

To optimize memory performance and flexibility, both paging and bank interleaving are supported in the DRAM controller.  Page mode may be enabled or disabled for each pair of DRAM banks independently.  The bank interleaving feature is automatically enabled when each pair of DRAM banks uses the same type DRAMs.  If two banks of memory have the same type DRAMs, then 2-way interleaving is performed and if all four banks of memory have the same type DRAMs, 4-way interleaving is enabled. In the case of using the different type DRAM in one bank (logical bank 0 and 1, or bank 2 and 3), the bank interleaving for that bank is disabled and linear memory addressing is performed.

While the bank interleaving is used automatically, two methods of interleaving may be used.  One method is word interleaving which occurs on address bit 1, another is block interleaving which occurs on address bit 10.  The default memory configuration is page mode and block interleaving enabled with fast page-mode 80ns DRAMs.

The exact memory configuration installed is determined during system initialization through execution of a memory autoscan routine of Power-On Self Test in the system BIOS.  Relevant memory configuration information is then programmed into the memory configuration registers.


Expanded Memory Specification (EMS) Support

The EMS system consists of 72 mapping registers which are split into a standard and alternate set of 36 registers each.  The memory controller can support LIM EMS 4.0 specification with any of valid memory maps of 1M Bytes and higher.  The alternate register set allows rapid hardware context switching.

The EMS system is split into two parts, 12 EMS page registers which covers range from C0000h to EFFFFh and 24 backfill registers that cover 40000h to 9FFFFh.  Bit D7 of configuration register EMSEN1 is a global enable for the EMS page registers.  Each of 12 EMS page registers can then be individually disabled if there are system address conflicts.  Bits 0-7 of EMSEN2 and bits 0-3 of EMSEN1 are used to support this function. 24 EMS backfill registers are enabled by setting bit 6 of EMSEN1.  These registers are all enabled or all disabled - no individual control is provided.  If a full LIM EMS 4.0 system is desired, both bits 6 and 7 of EMSEN1 are set as are the desired EMS page register enable bits.  When the backfill registers are not used, the EMS driver allocates all memory above SLTPTR for EMS page memory.  It also can use the system board memory at the same address as the enabled EMS page registers and any other 16K segments in the A0000h-BC000h and F0000h-FC000h areas for which the shadow code is 00b as set in configuration registers AAXS, BAXS, and FAXS.  When the backfill registers are active EMS pages can also be allocated for all system board memory from 40000h to 9FFFFh.  There is no wasted DRAM in a system memory controller-based system.


DMA CONTROLLER

The Direct Memory Access (DMA) Controller is used to transfer data directly between memory and I/O devices.  This controller is included in the 82C331 chip on the system board, which is fully compatible with Intel 8237A DMA Controller.  The system provides eight DMA channels, seven of which are available.  Channels  0 through 3 transfer 8-bit data between 8-bit I/O devices and either 8-bit or 16-bit memory across the entire system memory in 64Kb blocks.  Channels 5 through 7 are cascaded to the CPU by channel 4 and transfer 16-bit data across the entire system memory in 128Kb blocks.  The following table lists DMA channel assignments:

Channel	Controller	Function
0	1	Spare
1	1	Spare
2	1	Floppy Disk
3	1	Fixed Disk
4	2	Cascade
5	2	Spare
6	2	Spare
7	2	Spare


System Timers

The system has three programmable timer/counters.  The assignments of each channel are described as follows:

Channel 0	IRQ 0 of Interrupt Controller (System Timer)

Channel 1	Request Refresh Cycle

Channel 2	Tone Generator for Speaker

These channels are controlled by the Intel 8254-2 contained within the Intel 82C331 chip on the system baseboard.


Power-On Self Test (POST)

Each time the system is powered on, the built-in POST runs automatically and checks the system board, CPU, system timers and logic devices, keyboard, and memory.  POST also checks most peripheral devices such as the on-board video controller and mass storage devices.

During the POST memory test, the amount of memory being tested is displayed on the screen.  Depending on the amount of extended memory installed, the POST memory test takes 5 to 60 seconds to complete.

If POST does not find any errors, the system beeps once and displays the normal sign-on message.  If POST finds an error and cannot display a message, the system speaker emits a series of beeps to indicate the error and places a value in I/O port 80H.  No beep code is sounded if a test is aborted in progress.  Many beep codes indicate problems which can only be solved by replacing or repairing boards or other system components.  See the following for more information on beep codes:

Beep Codes (Fatal Errors)	Beep Codes (Non-Fatal Errors)


REGULATORY CERTIFICATIONS

The Model LP386SX-20 meets or exceeds each of the following regulatory standards:

Safety

US	UL1950

Canada	CSA C22.2 No. 950

Europe	TUV EN 60950 with ZH1/618 Ergonomics,

IEC 950 and IEC 380

EMI/RFI

US	FCC CFR 47 Part 15, Class B

Canada	DOC CRC c.1374 Class B

Europe	VDE 0871 Class B


Product Order Codes

The following order codes represent available configurations of the LP386SX-20 microcomputer:

Order Codes:	Description:

LP386SX20I2N	2MB memory, no floppy or hard disks

LP386SX20I2F	2MB memory, 3.5" floppy

LP386SX20I2I	2MB memory, 3.5" floppy, 52MB IDE HD


Model LP386SX-20 Additional Information Menu

System Specifications	System Interrupts

Jumper Settings	Memory Map

I/O Addresses	Beep Codes (Fatal Errors)

Baseboard Connector Locations	Beep Codes (Non-Fatal Errors)


SYSTEM SPECIFICATIONS

Physical Dimensions

Height	3.86 inches  (9.9 cm)

Width	15.4 inches  (39.1 cm)

Depth	15.8 inches  (40.1 cm)

Weight	17 lbs  (7.7 kg) without peripherals

Cables

Power Cable : 	Approximately 2.0 meter (Shielded cable)

Air Temperature

System Operating : 	10 to 35 degrees C

System Non-Operating : 	-40 to 70 degrees C

Humidity

System Operating : 	20% to 80% at 35 C

System Non-Operating : 	92% at 55 C

Altitude

System Operating : 	10,000 feet

System Non-Operating : 	50,000 feet

Acoustical Noise

System Operating : 	42 db at 1 meter

System Peripherals Idling : 	37 db at 1 meter

Electrical (Switch Selectable)

Low Range : 	90 - 132 VAC

High Range : 	187 - 264 VAC

Calculated MTBF Data (System Configuration at 40 degrees C)

LP386SX20I2I	10,000 hours

LP386SX20I2F	14,000 hours

LP386SX20I2N	21,000 hours


Jumper Settings

The following jumper settings indicate the possible configuration combinations located on the baseboard (bold-type values are the factory-set defaults):

On-board VGA controller Enable	(J3 : IN)

On-board HDD, FDC, SIO and PIO Enable	(J9 : IN)

Primary display adapter attached	(J8 : IN - Color)

Printer interrupt select	(J23 : 1-2 - IRQ7)

On-board mouse interrupt (IRQ12) enable	(J24 : IN)

The following jumper settings are used only for factory testing and should not be changed:

Manufacturing test support	(J14 : OUT - Disable)

Base memory size for manufacturing test	(J13 : OUT - 640KB)


I/O ADDRESSES

The following table shows hex addresses for each of the system board I/O functions:

Address	I/O Function
0000-001F	DMA Controller, Channels 0-3
0020-0021	Interrupt Controller 1
0040-0043	System Timers
0060	Keyboard, Mouse
0061-006F (odd bytes)	System Control Port B
0064	Keyboard, Mouse
0070,0071	RTC/CMOS and NMI Mask
0081,0082,0083,0087	DMA Page Registers (0-3)
0089,008A,008B,008F	DMA Page Registers (5-7)
0090	Central Arbitration Control Port
0091	Card Select Feed back
0092	System Control Port A
0094	System Board Enable/Setup Register
0096	Adapter Enable/Setup Register
00A0-00A1	Interrupt Controller 2
00C0-00DE (even bytes)	DMA Controller, Channels 4-7
00F0-00FF	Math Coprocessor
0100-0107	Programmable Option Select
01F0-01F8	Hard Disk Drive Controller
0278-027A	Parallel Port 3
02F8-02FF	Serial Port 2 (RS-232C)
0378-037A	Parallel Port 2
03BC-03BE	Parallel Port 1
03B4-03BA	Video Subsystem
03F0-03F7	Diskette Drive Controller
03F8-03FF	Serial Port 1 (RS-232C)


Baseboard Connector Locations

The following table lists the system baseboard connector types and numbers:

Connector	Number
PS/2 Keyboard connector	J16
PS/2 Mouse connector	J15
25 Pin Parallel port connector	J7
9 Pin Serial port connector	J4
15 pin Video Display connector	J2
I/O expansion board interface	J5 & J6
Power supply connector	PS1
Floppy disk drive connector	J12
Fixed-disk drive AT interface	J11
SIMM memory module sockets	U1-U8
80387SX-25 math co-processor	U21
Power-On LED connector	J19
HDD access LED connector	J22
Speaker connector	J21
Hardware reset switch connector	J20
Keyboard lock connector	J18
Backup battery connector	J10


SYSTEM INTERRUPTS

There are three signals for interrupts in the system: RESET, NMI (Non-Maskable Interrupt), and INTR (Maskable System Interrupts).  RESET has the highest priority among these signals and places the CPU in it's known initial state.  NMI is an interrupt that can not be masked by software.  The system provides 15 levels of system interrupts which may be masked.  The controller for these maskable interrupts is included in the 82C331 chip on the system board, which is fully compatible with Intel 8259A Interrupt Controller.  The following table lists the interrupt levels and their functions in the order of their priority:

Priority	Level	Function
1	NMI	Parity error detected
2	IRQ0	Timer, counter output 0
3	IRQ1	Keyboard (Output Buffer Full)
4	IRQ8	Real Time Clock
5	IRQ9	Redirect Cascade
6	IRQ10	Reserved
7	IRQ11	Reserved
8	IRQ12	Auxiliary Device
9	IRQ13	Math Coprocessor Exception
10	IRQ14	Fixed-Disk Controller
11	IRQ15	Reserved
12	IRQ3	Serial Alternate
13	IRQ4	Serial Primary
14	IRQ5	Reserved
15	IRQ6	Floppy Disk Controller
16	IRQ 7	Parallel Port

The Non-Maskable Interrupt (NMI) can be generated by a parity error on the on-board memory or a I/O channel check error.  The NMI masks all other interrupts and the IRET instruction restores the interrupt flag to the state it was in prior to the interrupt.  The NMI is reset by a system reset.

The system uses two interrupt controllers to process hardware interrupts.  The controller 1 is located at I/O addresses 0020 0021h and is programmed in the fully nested mode for master operation.  The I/O addresses of the controller 2 are 00A0h 00A1h.  The IRQ2 of the master controller is cascaded to the controller 2 to support 15 levels of interrupts.


Memory Map

The following table describes the LP386SX-20 system memory map:

Address (Hex)	Size	Function
000000 - 09FFFF	640Kb	Main Memory on System Board
0A0000 - 0BFFFF	128Kb	Reserved for Video RAM
0C0000 - 0DFFFF	128Kb	Reserved for I/O Expansion ROM
0E0000 - 0FFFFF	128Kb	Reserved for System BIOS ROM
100000 - FDFFFF	15Mb	Extended Memory on System Board *
FE0000 - FFFFFF	128Kb	Reserved for Duplicate System BIOS
When 1Mb DRAM SIMMs are used the maximum size of extended memory that can be supported on the baseboard is 8Mb.  When 4Mb DRAM SIMMs are used, the total memory on the system board can be expanded up to 32Mb, with 16Mb expanded and 16Mb extended memory.


Beep Codes (Fatal Errors)

The table below lists the beep codes and the values POST writes to I/O port 80H when it encounters fatal error conditions(which halt the system):

Beep Code	Description of Error	I/O Port 80H
none	386 register test in progress	01H
1-1-3	Real-time clock write/read failure	02H
1-1-4	ROM BIOS checksum failure	03H
1-2-1	Programmable interval timer failure	04H
1-2-2	DMA initialization failure	05H
1-2-3	DMA page register write/read failure	06H
1-3-1	RAM refresh verification failure	08H
none	1st 64Kb RAM test in progress	09H
1-3-3	1st 64Kb RAM chip or data line failure multi-bit	0AH
1-3-4	1st 64Kb RAM odd/even logic failure	0BH
1-4-1	1st 64Kb RAM address line failure	0CH
1-4-2	1st 64Kb RAM parity test in progress or failure	0DH
2-1-1	Bit 0 1st 64Kb RAM failure	10H
2-1-2	Bit 1 1st 64Kb RAM failure	11H
2-1-3	Bit 2 1st 64Kb RAM failure	12H
2-1-4	Bit 3 1st 64Kb RAM failure	13H
2-2-1	Bit 4 1st 64Kb RAM failure	14H
2-2-2	Bit 5 1st 64Kb RAM failure	15H
2-2-3	Bit 6 1st 64Kb RAM failure	16H
2-2-4	Bit 7 1st 64Kb RAM failure	17H
2-3-1	Bit 8 1st 64Kb RAM failure	18H
2-3-2	Bit 9 1st 64Kb RAM failure	19H
2-3-3	Bit A 1st 64Kb RAM failure	1AH
2-3-4	Bit B 1st 64Kb RAM failure	1BH
2-4-1	Bit C 1st 64Kb RAM failure	1CH
2-4-2	Bit D 1st 64Kb RAM failure	1DH
2-4-3	Bit E 1st 64Kb RAM failure	1EH
2-4-4	Bit F 1st 64Kb RAM failure	1FH
3-1-1	Slave DMA register failure	20H
3-1-2	Master DMA register failure	21H
3-1-3	Master interrupt mask register failure	22H
3-1-4	Slave interrupt mask register failure	23H
none	Interrupt vector loading in progress	25H
3-2-4	Keyboard controller test failure	27H
none	Real-time clock power failure or checksum failure	28H


Beep Codes (Non-Fatal Errors)

The table below lists the beep codes and the values POST writes to I/O port 80H when it encounters non-fatal error conditions(which do not halt the system):

Beep Code	Description of Error	I/O Port 80H
none	Real-time clock configuration	29H
3-3-4	Screen memory test failure	2BH
3-4-1	Screen initialization failure	2CH
3-4-2	Screen retrace failure	2DH
none	Search for video ROM in progress	2EH
none	Screen running with video ROM	30H
none	Monochrome display operable	31H
none	Color display (40 column) operable	32H
none	Color display (80 column) operable	33H


Model LP386SX-20 Board Product History
Board Product History

October, 1992

Board Assembly A611521B

Rev. 1.1	effective June 1991

PCB Part Number	611-521A0

BIOS version	1.10 17.T0

Comments:

1) This was the first production version of the LP386SX-20 board assembly.

Rev. 1.2	effective July 1991

PCB Part Number	611-521A1

BIOS version	1.10 17.T0

Comments:

1) PCB artwork altered to move two 100pF capacitors (U24, J6) from solder side to the component side (C182, C183) for auto-insertion.

Rev. 1.3	effective August 1991

PCB Part Number	611-521A1

BIOS version	1.10 17.T0

Comments:

1) Fuse changed from 125V/2A to 125V/3A slow-blow type to improve reliability.

2) Stepping change of the Intel 82344 PC/AT Bus Controller (VL82C331) from x1000 to x2000.

Rev. 1.4	effective December 1991

PCB Part Number	611-521A1

BIOS version	1.10 18.T0

Comments:

1) VRAM changed from 80nS to 70nS and VRAM clock changed from 37.585 MHz to 41.612 MHz by adding resistor (R153) for enhanced video performance.

2) BIOS EPROMS (U9, U10) changed from V1.10 17.T0 to V1.10 18.T0.

Rev. 1.5	effective January 1992

PCB Part Number	611-521A1

BIOS version	1.10 18.T0

Comments:

1) Stepping changes of the 82343 PC/AT System Controller (from VL82C320 x5000 to VL82C320A x2000) and the 82344 PC/AT Bus Controller (VL82C331 x2000 to x3000).

2) Change of resistors R67, 70, 72, 75, 79, 84, 88, 93, 96, 102, 107, and 111 from 22 ohm to 10 ohm as a result of design review to improve performance of memory addressing.

Rev. 1.6	effective February 1992

PCB Part Number	611-521A2

BIOS version	1.10 18.T0

Comments:

1) Added 100 ohm pull-down resistor (R159) and 10K ohm pull-up resistor (R160).

Rev. 1.7	effective March 1992

PCB Part Number	611-521A2

BIOS version	1.10 18.T0

Comments:

1) Stepping change of the 80386SX-20 CPU from "C" to "D".

Rev. 1.8	effective April 1992

PCB Part Number	611-521A2

BIOS version	1.10 19.T0

Comments:

1) Changed ferrite bead (L18) to lower value to fix hard disk drive boot problem when using Future Domain SCSI add-in board (TMC-1680) and Western Digital Ethernet board (WD8003E).

2) BIOS EPROMs (U9, U10) changed from V1.10 18.T0 to V1.10 19.T0.

Rev. 1.9	effective May 1992

PCB Part Number	611-521A2

BIOS version	1.10 21.T0

Comments:

1) BIOS EPROMS (U9, U10) changed from V1.10 19.T0 to V1.10 21.T0.

Rev. 2.0	effective August 1992

PCB Part Number	611-521A2

BIOS version	1.10 23.T0

Comments:

1) BIOS EPROMS (U9, U10) changed from V1.10 21.T0 to V1.10 23.T0.

Rev. 2.1	effective September 1992

PCB Part Number	611-521B0

BIOS version	1.10 24.T0

Comments:

1) BIOS EPROMS (U9, U10) changed from V1.10 23.T0 to V1.10 24.T0.

2) DIN connector changed from non-ESD to ESD type.

3) PCB changed due to re-routing of the master clock line for EMI considerations under 25MHz operation.

4) PC/AT chipset was changed from 20MHz type to 25MHz type which allows the LP386SX-20 and LP386SX-25 to use the same baseboard.


Model LP386SX-20 System Product History
System Product History

October, 1992

Product Codes and Features:

Product Code	TA Number	Features
LP386SX20I2N	514822-xxx	2Mb memory, no floppy or hard disk drives
LP386SX20I2F	514823-xxx	2Mb, 3.5" floppy, no hard disk
LP386SX20I2I	514824-xxx	2Mb, 3.5" floppy, 52Mb or 80Mb hard disk

General Information:

Production Released in June 1991.  There are no AA, CBA, or PBA numbers used with this system.  The current Top Assembly (TA) number is 51482x-015 which includes the Rev. 2.1 Board Assembly and V1.10 24.T0 BIOS.  See either the Board History or BIOS History sections for details regarding those subsystems.

System History:

TA 51482x-001	effective June 1991

Board Assembly	Rev. 1.1

Power Supply	Rev. E

BIOS revision	V1.10 17.T0

Comments:

1) Production release.

TA 51482x-002	effective July 1991

Board Assembly	Rev. 1.2

Power Supply	Rev. E

BIOS revision	V1.10 17.T0

Comments:

1) Changes to PCB layout for improved manufacturability.

TA 51482x-003	effective August 1991

Board Assembly	Rev. 1.3

Power Supply	Rev. E

BIOS revision	V1.10 17.T0

Comments:

1) Split ferrite core was deleted from video cable since it was not needed for FCC certification.  The errata sheet which explained the reason for the ferrite core was also removed.

2) Component changes on board assembly.

TA 51482x-004	effective October 1991

Board Assembly	Rev. 1.3

Power Supply	Rev. E

BIOS revision	V1.10 17.T0

Comments:

1) Bottom chassis assembly modified for EMI clips change.

TA 51482x-005	effective December 1991

Board Assembly	Rev. 1.4

Power Supply	Rev. E

BIOS revision	V1.10 18.T0

Comments:

1) New BIOS revision V1.10 18.T0 to fix known problems.

2) Component changes on board assembly.

3) Removed two-pin header on the expansion slot board (Rev. 1.0 to Rev. 1.1).

TA 51482x-006	effective January 1992

Board Assembly	Rev. 1.5

Power Supply	Rev. E

BIOS revision	V1.10 18.T0

Comments:

1) Component changes on board assembly.

TA 51482x-007	effective February 1992

Board Assembly	Rev. 1.5

Power Supply	Rev. F

BIOS revision	V1.10 18.T0

Comments:

1) Power supply change from Rev. E to Rev. F to meet DEMKO regulatory requirements.

TA 51482x-008	effective February 1992

Board Assembly	Rev. 1.6

Power Supply	Rev. F

BIOS revision	V1.10 18.T0

Comments:

1) Changes to PCB layout for added components.

TA 51482x-009	effective February 1992

Board Assembly	Rev. 1.6

Power Supply	Rev. G

BIOS revision	V1.10 18.T0

Comments:

1) Power supply change from Rev. F to Rev. G to eliminate broadband radiation in the 80MHz to 150MHz frequency range.

TA 51482x-010	effective March 1992

Board Assembly	Rev. 1.7

Power Supply	Rev. G

BIOS revision	V1.10 18.T0

Comments:

1) Component changes on board assembly.

2) Floppy disk drive changed to TEAC model FD235HF-3269 due to phase out of model FD235HF-269.

TA 51482x-011	effective April 1992

Board Assembly	Rev. 1.8

Power Supply	Rev. G

BIOS revision	V1.10 19.T0

Comments:

1) Component changes on board assembly.

2) New BIOS revision V1.10 19.T0 to fix known problem.

TA 51482x-012	effective May 1992

Board Assembly	Rev. 1.9

Power Supply	Rev. G

BIOS revision	V1.10 21.T0

Comments:

1) New BIOS revision V1.10 21.T0 to fix known problem.

TA 51482x-013	effective July 1992

Board Assembly	Rev. 1.9

Power Supply	Rev. G

BIOS revision	V1.10 21.T0

Comments:

1) Change of caution label on power supply AC line cord socket.

2) Addition of warning card to literature kit advising Nordic customers to change fuse and fuse holder to meet SEMKO requirements.

TA 51482x-014	effective August 1992

Board Assembly	Rev. 2.0

Power Supply	Rev. G

BIOS revision	V1.10 23.T0

Comments:

1) Chassis modification and new I/O bracket to fix keyboard/mouse port alignment problem.

2) Replacement of Quantum 52Mb (setup type 25) hard disk drive with either Conner 80Mb (setup type 45) or Maxtor 80Mb (setup type 47) hard disk drive.

3) New BIOS revision V1.10 23.T0 to add new drive types to setup table.

TA 51482x-015	effective September 1992

Board Assembly	Rev. 2.1

Power Supply	Rev. H

BIOS revision	V1.10 24.T0

Comments:

1) Power supply change from Rev. G to Rev. H to replace 0.5W resistors (R5, R6) with 1.0W resistors for improved headroom.

2) EMI clips removed from I/O bracket.

3) Changes to PCB and components on board assembly.

4) New BIOS revision V1.10 24.T0 to fix known problems.


Model LP386SX-20 Orderable Spare Parts List
Orderable Spare Parts

October 1992

PART NUMBER	DESCRIPTION

109889-080	1Mb x 9 SIMM

S301K4PS2	Keyboard

SPRA151060A	Floppy Drive, 2Mb, 3.5"

SPRA153072A	Hard Drive, 52Mb, 3.5" LPS

SPRA611514A	Mother Board, 16MHz, 1Mb

SPRA611514B	Mother Board, 16MHz, 2Mb

SPRA611521B	Mother Board, 20MHz, 2Mb

A611521C	Mother Board, 25MHz, 2Mb

SPRA611596D	Slot Board, I/O, 4-layer

SPRA634105E	Power Supply, 114 Watt

472-333A	Rubber Feet

SPR1MPB1830L	Screw, MP 3 x 6, MSWR3/FN

SPR215-442B	Top Cover

SPR227-232A	Back Panel Card Cage Guide

SPR235-481A	Floppy Disk Bracket

SPR235-482A	Hard Disk Bracket

SPR285-016A	Rod, Power Switch

SPR313-186A	Bushing, Grommet

SPR316-232A	Screw, UNC 6-32, L5.5 PHIPS

SPR317-072A	Screw, HEX, Taptite-B3 x 8FN

SPR421-604B	Plate Connector

SPR522-084A	Front 3.5" Blank Panel

SPR632-028A	Battery, 3.6V

SPR668-059B	Power Cord

SPRA221086C	Base Assy.

SPRA261020A	Keylock Assy.

SPRA522099A	Bezel, Front Assy. 3.5" FDD

SPRA522100A	Bezel, Front Assy., 3.5" FDD, Bezel

SPRA611516A	PCB LED

SPRA644239F	Ground Cable

SPRA644544A	`	Floppy Cable 3.5" Drive

SPRA644681B	Hard Drive Cable (40-pin)

SPRA651130A	Reset Switch Assy.

SPRA691009H	Speaker Assy. w/connector


Model LP386SX-20 BIOS History
BIOS History

October, 1992

TA 51482x-xxx System BIOS

The LP386SX-20 system BIOS is contained in two D27C512-200V10 EPROM devices at locations U9 (odd) and U10 (even) on the board assembly.

Version V1.10 17.T0	effective June, 1991

Comments:

1) Initial production release of the System BIOS.

Version V1.10 18.T0	effective December, 1991

Comments:

1) Fixed a hard disk drive problem which occurred when configuring with QEMM and EMM386 under DOS 5.0.

2) Fixed a CTRL-ALT-DEL reboot problem which occurred under DOS 5.0 if LOADHIGH was used to place a keyboard driver into high memory.

Version V1.10 19.T0	effective April, 1992

Comments:

1) Fixed a problem with the initial memory size check which occurred following power-on when using GSEN 3-chip SIMMs.

Version V1.10 21.T0	effective May, 1992

Comments:

1) Fixed a co-processor problem which occurred when running an Intel diagnostic program (RUNMCP.EXE).


Version V1.10 23.T0	effective August, 1992

Comments:

1) Added Conner 80Mb (setup type 45) and Maxtor 80Mb (setup type 47) hard disk drive types.

Version V1.10 24.T0	effective September, 1992

Comments:

1) New Phoenix source base.

2) Fixed DOS 5.0 logical disk format problem.

3) Fixed password re-boot problem - CTRL-ALT-DEL no longer bypasses the password security feature.

4) Added compatibility with Everex video adapter boards and TSENG Labs chipset.

5) Drive B: made available as a single drive option.  It is not necessary to have Drive A: in order to have a logical Drive B:.